Searched refs:vMPLL_SS2 (Results 1 - 17 of 17) sorted by relevance

/openbsd-current/sys/dev/pci/drm/radeon/
H A Drv770_smc.h55 uint32_t vMPLL_SS2; member in struct:RV770_SMC_MCLK_VALUE
70 uint32_t vMPLL_SS2; member in struct:RV730_SMC_MCLK_VALUE
H A Dnislands_smc.h81 uint32_t vMPLL_SS2; member in struct:NISLANDS_SMC_MCLK_VALUE
H A Drv730_dpm.c190 mclk->mclk730.vMPLL_SS2 = cpu_to_be32(mpll_ss2);
336 table->initialState.levels[0].mclk.mclk730.vMPLL_SS2 =
H A Dsislands_smc.h123 uint32_t vMPLL_SS2; member in struct:SISLANDS_SMC_MCLK_VALUE
H A Drv740_dpm.c282 mclk->mclk770.vMPLL_SS2 = cpu_to_be32(mpll_ss2);
H A Dcypress_dpm.c608 mclk->mclk770.vMPLL_SS2 = cpu_to_be32(mpll_ss2);
1261 table->initialState.levels[0].mclk.mclk770.vMPLL_SS2 =
H A Drv770_dpm.c1047 table->initialState.levels[0].mclk.mclk770.vMPLL_SS2 =
H A Dni_dpm.c1704 table->initialState.level.mclk.vMPLL_SS2 =
2293 mclk->vMPLL_SS2 = cpu_to_be32(mpll_ss2);
H A Dsi_dpm.c4372 table->initialState.level.mclk.vMPLL_SS2 =
4574 table->ACPIState.level.mclk.vMPLL_SS2 =
4938 mclk->vMPLL_SS2 = cpu_to_be32(mpll_ss2);
/openbsd-current/sys/dev/pci/drm/amd/pm/powerplay/hwmgr/
H A Dsmu7_hwmgr.h127 uint32_t vMPLL_SS2; member in struct:smu7_clock_registers
H A Dsmu7_hwmgr.c4819 data->clock_registers.vMPLL_SS2 =
/openbsd-current/sys/dev/pci/drm/amd/pm/legacy-dpm/
H A Dsislands_smc.h119 uint32_t vMPLL_SS2; member in struct:SISLANDS_SMC_MCLK_VALUE
H A Dsi_dpm.h386 uint32_t vMPLL_SS2; member in struct:RV770_SMC_MCLK_VALUE
401 uint32_t vMPLL_SS2; member in struct:RV730_SMC_MCLK_VALUE
739 uint32_t vMPLL_SS2; member in struct:NISLANDS_SMC_MCLK_VALUE
H A Damdgpu_si_dpm.c4851 table->initialState.level.mclk.vMPLL_SS2 =
5077 table->ACPIState.level.mclk.vMPLL_SS2 =
5440 mclk->vMPLL_SS2 = cpu_to_be32(mpll_ss2);
/openbsd-current/sys/dev/pci/drm/amd/pm/powerplay/smumgr/
H A Diceland_smumgr.c1062 uint32_t mpll_ss2 = data->clock_registers.vMPLL_SS2;
1545 PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_SS2);
H A Dci_smumgr.c1040 uint32_t mpll_ss2 = data->clock_registers.vMPLL_SS2;
1499 PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_SS2);
H A Dtonga_smumgr.c805 uint32_t mpll_ss2 = data->clock_registers.vMPLL_SS2;
1287 PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_SS2);

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