Searched refs:uclk (Results 1 - 17 of 17) sorted by relevance

/openbsd-current/sys/dev/pci/drm/amd/pm/swsmu/smu12/
H A Dsmu_v12_0.c343 smu->smu_table.boot_values.uclk = v_3_1->bootup_mclk_in10khz;
360 smu->smu_table.boot_values.uclk = v_3_3->bootup_mclk_in10khz;
H A Drenoir_ppt.c199 * This interface just for getting uclk ultimate freq and should't introduce
293 clock_limit = smu->smu_table.boot_values.uclk;
/openbsd-current/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/
H A Ddcn32_clk_mgr.c540 !dc->work_arounds.clock_update_disable_mask.uclk) {
580 !dc->work_arounds.clock_update_disable_mask.uclk) {
588 !dc->work_arounds.clock_update_disable_mask.uclk) {
/openbsd-current/sys/dev/pci/drm/amd/pm/swsmu/smu11/
H A Dsmu_v11_0.c555 smu->smu_table.boot_values.uclk = v_3_1->bootup_mclk_in10khz;
572 smu->smu_table.boot_values.uclk = v_3_3->bootup_mclk_in10khz;
836 max_sustainable_clocks->uclock = smu->smu_table.boot_values.uclk / 100;
1709 clock_limit = smu->smu_table.boot_values.uclk;
H A Dvangogh_ppt.c945 clock_limit = smu->smu_table.boot_values.uclk;
H A Darcturus_ppt.c382 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;
717 * But this is available for gfxclk/uclk/socclk/vclk/dclk.
H A Dnavi10_ppt.c1012 /* uclk dpm table setup */
1024 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;
2112 dev_err(smu->adev->dev, "[%s] Set hard min uclk failed!", __func__);
2769 /* This workaround can be applied only with uclk dpm enabled */
2783 * This workaround is needed only when the max uclk frequency
H A Dsienna_cichlid_ppt.c979 /* uclk dpm table setup */
991 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;
1812 dev_err(smu->adev->dev, "[%s] Set hard min uclk failed!", __func__);
/openbsd-current/sys/dev/pci/drm/amd/pm/swsmu/smu13/
H A Dsmu_v13_0.c606 smu->smu_table.boot_values.uclk = v_3_1->bootup_mclk_in10khz;
620 smu->smu_table.boot_values.uclk = v_3_3->bootup_mclk_in10khz;
635 smu->smu_table.boot_values.uclk = v_3_4->bootup_mclk_in10khz;
890 max_sustainable_clocks->uclock = smu->smu_table.boot_values.uclk / 100;
1559 clock_limit = smu->smu_table.boot_values.uclk;
H A Dsmu_v13_0_5_ppt.c733 clock_limit = smu->smu_table.boot_values.uclk;
H A Dsmu_v13_0_4_ppt.c758 clock_limit = smu->smu_table.boot_values.uclk;
H A Dyellow_carp_ppt.c867 clock_limit = smu->smu_table.boot_values.uclk;
H A Daldebaran_ppt.c361 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;
699 * But this is available for gfxclk/uclk/socclk/vclk/dclk.
H A Dsmu_v13_0_0_ppt.c628 /* uclk dpm table setup */
638 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;
894 /* uclk dpm table */
H A Dsmu_v13_0_7_ppt.c618 /* uclk dpm table setup */
628 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;
875 /* uclk dpm table */
/openbsd-current/sys/dev/pci/drm/amd/pm/swsmu/inc/
H A Damdgpu_smu.h284 uint32_t uclk; member in struct:smu_bios_boot_up_values
/openbsd-current/sys/dev/pci/drm/amd/display/dc/
H A Ddc.h286 uint8_t uclk : 1; member in struct:dc_bug_wa::__anon10

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