Searched refs:smu_print (Results 1 - 8 of 8) sorted by relevance
/openbsd-current/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/ |
H A D | dcn30_clk_mgr_smu_msg.c | 47 #define smu_print(str, ...) {DC_LOG_SMU(str, ##__VA_ARGS__); } macro 114 smu_print("SMU Test message: %d\n", input); 126 smu_print("SMU Get SMU version\n"); 131 smu_print("SMU version: %d\n", *version); 144 smu_print("SMU Check driver if version\n"); 149 smu_print("SMU driver if version: %d\n", response); 163 smu_print("SMU Check msg header version\n"); 168 smu_print("SMU msg header version: %d\n", response); 179 smu_print("SMU Set DRAM addr high: %d\n", addr_high); 187 smu_print("SM [all...] |
/openbsd-current/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/ |
H A D | dcn32_clk_mgr_smu_msg.c | 42 #define smu_print(str, ...) {DC_LOG_SMU(str, ##__VA_ARGS__); } macro 95 smu_print("FCLK P-state support value is : %d\n", enable); 106 smu_print("Numways for SubVP : %d\n", num_ways); 111 smu_print("SMU Transfer WM table DRAM 2 SMU\n"); 119 smu_print("SMU Set PME workaround\n"); 133 smu_print("SMU Set hard min by freq: clk = %d, freq_mhz = %d MHz\n", clk, freq_mhz); 138 smu_print("SMU Frequency set = %d KHz\n", response); 145 smu_print("PMFW to wait for DMCUB ack for MCLK : %d\n", enable);
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/openbsd-current/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/ |
H A D | dcn301_smu.c | 48 #define smu_print(str, ...) {DC_LOG_SMU(str, ##__VA_ARGS__); } macro 106 smu_print("SMU Response was not OK. SMU response after wait received is: %d\n", result); 184 smu_print("actual_dcfclk_set_mhz %d is set to : %d\n", actual_dcfclk_set_mhz, actual_dcfclk_set_mhz * 1000);
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/openbsd-current/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn21/ |
H A D | rn_clk_mgr_vbios_smu.c | 48 #define smu_print(str, ...) {DC_LOG_SMU(str, ##__VA_ARGS__); } macro 106 smu_print("SMU Response was not OK. SMU response after wait received is: %d\n", result); 189 smu_print("actual_dcfclk_set_mhz %d is set to : %d\n", actual_dcfclk_set_mhz, actual_dcfclk_set_mhz * 1000);
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/openbsd-current/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/ |
H A D | dcn315_smu.c | 76 #define smu_print(str, ...) {DC_LOG_SMU(str, ##__VA_ARGS__); } macro 142 smu_print("SMU Response was not OK. SMU response after wait received is: %d\n", result); 165 smu_print("SMU msg id write fail %x times. \n", i + 1); 219 smu_print("actual_dcfclk_set_mhz %d is set to : %d\n", actual_dcfclk_set_mhz, actual_dcfclk_set_mhz * 1000);
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/openbsd-current/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/ |
H A D | dcn314_smu.c | 62 #define smu_print(str, ...) {DC_LOG_SMU(str, ##__VA_ARGS__); } macro 128 smu_print("SMU Response was not OK. SMU response after wait received is: %d\n", 224 smu_print("actual_dcfclk_set_mhz %d is set to : %d\n",
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/openbsd-current/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/ |
H A D | dcn316_smu.c | 63 #define smu_print(str, ...) {DC_LOG_SMU(str, ##__VA_ARGS__); } macro 127 smu_print("SMU Response was not OK. SMU response after wait received is: %d\n", result); 193 smu_print("actual_dcfclk_set_mhz %d is set to : %d\n", actual_dcfclk_set_mhz, actual_dcfclk_set_mhz * 1000);
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/openbsd-current/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/ |
H A D | dcn31_smu.c | 47 #define smu_print(str, ...) {DC_LOG_SMU(str, ##__VA_ARGS__); } macro 113 smu_print("SMU Response was not OK. SMU response after wait received is: %d\n", result); 206 smu_print("actual_dcfclk_set_mhz %d is set to : %d\n", actual_dcfclk_set_mhz, actual_dcfclk_set_mhz * 1000);
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