/openbsd-current/sys/dev/pci/drm/amd/display/dc/dce110/ |
H A D | dce110_opp_regamma_v.c | 42 set_reg_field_value( 48 set_reg_field_value( 55 set_reg_field_value( 61 set_reg_field_value( 91 set_reg_field_value( 105 set_reg_field_value( 137 set_reg_field_value( 143 set_reg_field_value( 154 set_reg_field_value( 165 set_reg_field_value( [all...] |
H A D | dce110_opp_csc_v.c | 119 set_reg_field_value( 130 set_reg_field_value( 136 set_reg_field_value( 148 set_reg_field_value( 154 set_reg_field_value( 166 set_reg_field_value( 172 set_reg_field_value( 184 set_reg_field_value( 190 set_reg_field_value( 202 set_reg_field_value( [all...] |
H A D | dce110_timing_generator_v.c | 62 set_reg_field_value(value, 0, 72 set_reg_field_value(value, 1, 86 set_reg_field_value(value, 0, 88 set_reg_field_value(value, 0, 104 set_reg_field_value( 110 set_reg_field_value( 124 set_reg_field_value( 130 set_reg_field_value( 260 set_reg_field_value( 269 set_reg_field_value( [all...] |
H A D | dce110_timing_generator.c | 114 set_reg_field_value(regval, early_cntl, 134 set_reg_field_value( 159 set_reg_field_value( 164 set_reg_field_value( 169 set_reg_field_value( 264 set_reg_field_value(regval, 0, CRTC_COUNT_CONTROL, 268 set_reg_field_value(regval, 1, CRTC_COUNT_CONTROL, 390 set_reg_field_value(v_total_max, 395 set_reg_field_value(v_total_min, 400 set_reg_field_value(v_total_cnt [all...] |
H A D | dce110_transform_v.c | 89 set_reg_field_value( 94 set_reg_field_value( 103 set_reg_field_value( 108 set_reg_field_value( 119 set_reg_field_value( 124 set_reg_field_value( 133 set_reg_field_value( 138 set_reg_field_value( 165 set_reg_field_value(value, data->taps.h_taps - 1, 167 set_reg_field_value(valu [all...] |
H A D | dce110_mem_input_v.c | 49 set_reg_field_value(value, 1, 70 set_reg_field_value(value, temp, 84 set_reg_field_value(value, temp, 106 set_reg_field_value(value, temp, 120 set_reg_field_value(value, temp, 159 set_reg_field_value(value, 1, UNP_GRPH_ENABLE, GRPH_ENABLE); 172 set_reg_field_value(value, info->gfx8.num_banks, 175 set_reg_field_value(value, info->gfx8.bank_width, 178 set_reg_field_value(value, info->gfx8.bank_height, 181 set_reg_field_value(valu [all...] |
H A D | dce110_compressor.c | 87 set_reg_field_value(value, 3, LB_SYNC_RESET_SEL, LB_SYNC_RESET_SEL); 88 set_reg_field_value(value, 1, LB_SYNC_RESET_SEL, LB_SYNC_RESET_SEL2); 104 set_reg_field_value(value, 2, LB_SYNC_RESET_SEL, LB_SYNC_RESET_SEL); 105 set_reg_field_value(value, 0, LB_SYNC_RESET_SEL, LB_SYNC_RESET_SEL2); 146 set_reg_field_value(value, 0, FBC_CNTL, FBC_GRPH_COMP_EN); 147 set_reg_field_value(value, 1, FBC_CNTL, FBC_EN); 148 set_reg_field_value(value, 2, FBC_CNTL, FBC_COHERENCY_MODE); 151 set_reg_field_value( 161 set_reg_field_value(value, 1, FBC_COMP_MODE, FBC_RLE_EN); 162 set_reg_field_value(valu [all...] |
/openbsd-current/sys/dev/pci/drm/amd/display/dc/dce/ |
H A D | dce_audio.c | 296 set_reg_field_value(value, capable, 315 set_reg_field_value(value, latency_in_ms, 338 set_reg_field_value(value, latency_in_ms, 351 set_reg_field_value(value, 1, 354 set_reg_field_value(value, 1, 359 set_reg_field_value(value, 0, 374 set_reg_field_value(value, 1, 379 set_reg_field_value(value, 0, 384 set_reg_field_value(value, 0, 411 set_reg_field_value(valu [all...] |
H A D | dce_aux.c | 126 set_reg_field_value( 134 set_reg_field_value( 149 set_reg_field_value(
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H A D | dce_link_encoder.c | 632 set_reg_field_value(value, hpd_source, AUX_CONTROL, AUX_HPD_SEL); 633 set_reg_field_value(value, 0, AUX_CONTROL, AUX_LS_READ_EN); 640 set_reg_field_value(value, 1, 1649 set_reg_field_value(value, 1, DC_HPD_CONTROL, DC_HPD_EN); 1659 set_reg_field_value(value, 0, DC_HPD_CONTROL, DC_HPD_EN);
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/openbsd-current/sys/dev/pci/drm/amd/display/dc/dce112/ |
H A D | dce112_compressor.c | 119 set_reg_field_value( 126 set_reg_field_value( 150 set_reg_field_value( 157 set_reg_field_value( 164 set_reg_field_value( 171 set_reg_field_value( 197 set_reg_field_value( 204 set_reg_field_value( 233 set_reg_field_value( 240 set_reg_field_value( [all...] |
H A D | dce112_hw_sequencer.c | 91 set_reg_field_value( 97 set_reg_field_value( 103 set_reg_field_value(
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/openbsd-current/sys/dev/pci/drm/amd/display/dc/dce80/ |
H A D | dce80_timing_generator.c | 99 set_reg_field_value( 133 set_reg_field_value( 139 set_reg_field_value( 147 set_reg_field_value( 152 set_reg_field_value( 158 set_reg_field_value( 163 set_reg_field_value( 170 set_reg_field_value( 176 set_reg_field_value(
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/openbsd-current/sys/dev/pci/drm/amd/display/dc/dce60/ |
H A D | dce60_timing_generator.c | 99 set_reg_field_value( 139 set_reg_field_value( 144 set_reg_field_value( 150 set_reg_field_value( 155 set_reg_field_value( 162 set_reg_field_value( 168 set_reg_field_value(
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/openbsd-current/sys/dev/pci/drm/amd/display/dc/dce120/ |
H A D | dce120_hw_sequencer.c | 95 set_reg_field_value( 127 set_reg_field_value( 133 set_reg_field_value( 139 set_reg_field_value(
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H A D | dce120_timing_generator.c | 418 set_reg_field_value(value, 0, D1VGA_CONTROL, D1VGA_MODE_ENABLE); 419 set_reg_field_value(value, 0, D1VGA_CONTROL, D1VGA_TIMING_SELECT); 420 set_reg_field_value( 422 set_reg_field_value(value, 0, D1VGA_CONTROL, D1VGA_OVERSCAN_COLOR_EN); 635 set_reg_field_value( 647 set_reg_field_value( 936 set_reg_field_value( 946 set_reg_field_value(
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/openbsd-current/sys/dev/pci/drm/amd/display/dc/irq/dce60/ |
H A D | irq_service_dce60.c | 65 set_reg_field_value(
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/openbsd-current/sys/dev/pci/drm/amd/display/dc/irq/dcn303/ |
H A D | irq_service_dcn303.c | 71 set_reg_field_value(value, current_status ? 0 : 1, HPD0_DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY);
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/openbsd-current/sys/dev/pci/drm/amd/display/dc/irq/dcn20/ |
H A D | irq_service_dcn20.c | 151 set_reg_field_value(
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/openbsd-current/sys/dev/pci/drm/amd/display/dc/irq/dcn10/ |
H A D | irq_service_dcn10.c | 148 set_reg_field_value(
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/openbsd-current/sys/dev/pci/drm/amd/display/dc/irq/dce110/ |
H A D | irq_service_dce110.c | 55 set_reg_field_value(value, current_status ? 0 : 1,
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/openbsd-current/sys/dev/pci/drm/amd/display/dc/irq/dce120/ |
H A D | irq_service_dce120.c | 56 set_reg_field_value(
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/openbsd-current/sys/dev/pci/drm/amd/display/dc/irq/dce80/ |
H A D | irq_service_dce80.c | 56 set_reg_field_value(
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/openbsd-current/sys/dev/pci/drm/amd/display/dc/ |
H A D | dm_services.h | 112 #define set_reg_field_value(reg_value, value, reg_name, reg_field)\ macro
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/openbsd-current/sys/dev/pci/drm/amd/display/dc/irq/dcn201/ |
H A D | irq_service_dcn201.c | 99 set_reg_field_value(
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