Searched refs:requested_dpp_khz (Results 1 - 12 of 12) sorted by relevance
| /openbsd-current/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn21/ |
| H A D | rn_clk_mgr_vbios_smu.h | 37 int rn_vbios_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz);
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| H A D | rn_clk_mgr_vbios_smu.c | 218 int rn_vbios_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz) argument
225 khz_to_mhz_ceil(requested_dpp_khz));
227 ASSERT(actual_dppclk_set_mhz >= khz_to_mhz_ceil(requested_dpp_khz));
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| /openbsd-current/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/ |
| H A D | dcn301_smu.c | 204 int dcn301_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz) argument
208 DC_LOG_DEBUG("%s(%d)\n", __func__, requested_dpp_khz);
213 khz_to_mhz_ceil(requested_dpp_khz));
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| H A D | dcn301_smu.h | 155 int dcn301_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz);
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| /openbsd-current/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/ |
| H A D | dcn314_smu.h | 98 int dcn314_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz);
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| H A D | dcn314_smu.c | 250 int dcn314_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz) argument
255 return requested_dpp_khz;
260 khz_to_mhz_ceil(requested_dpp_khz));
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| /openbsd-current/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/ |
| H A D | dcn315_smu.h | 118 int dcn315_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz);
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| H A D | dcn315_smu.c | 243 int dcn315_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz) argument
248 return requested_dpp_khz;
253 khz_to_mhz_ceil(requested_dpp_khz));
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| /openbsd-current/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/ |
| H A D | dcn316_smu.c | 217 int dcn316_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz) argument
222 return requested_dpp_khz;
227 khz_to_mhz_ceil(requested_dpp_khz));
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| H A D | dcn316_smu.h | 126 int dcn316_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz);
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| /openbsd-current/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/ |
| H A D | dcn31_smu.c | 230 int dcn31_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz) argument
235 return requested_dpp_khz;
240 khz_to_mhz_ceil(requested_dpp_khz));
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| H A D | dcn31_smu.h | 259 int dcn31_smu_set_dppclk(struct clk_mgr_internal *clk_mgr, int requested_dpp_khz);
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