Searched refs:regSDMA0_QUEUE0_RB_CNTL (Results 1 - 4 of 4) sorted by relevance

/openbsd-current/sys/dev/pci/drm/amd/amdgpu/
H A Damdgpu_amdkfd_gfx_v11.c135 regSDMA0_QUEUE0_RB_CNTL) - regSDMA0_QUEUE0_RB_CNTL;
139 regSDMA1_QUEUE0_RB_CNTL) - regSDMA0_QUEUE0_RB_CNTL;
146 + queue_id * (regSDMA0_QUEUE1_RB_CNTL - regSDMA0_QUEUE0_RB_CNTL);
358 WREG32(sdma_rlc_reg_offset + regSDMA0_QUEUE0_RB_CNTL,
408 WREG32(sdma_rlc_reg_offset + regSDMA0_QUEUE0_RB_CNTL, data);
427 for (reg = regSDMA0_QUEUE0_RB_CNTL;
480 sdma_rlc_rb_cntl = RREG32(sdma_rlc_reg_offset + regSDMA0_QUEUE0_RB_CNTL);
547 temp = RREG32(sdma_rlc_reg_offset + regSDMA0_QUEUE0_RB_CNTL);
549 WREG32(sdma_rlc_reg_offset + regSDMA0_QUEUE0_RB_CNTL, tem
[all...]
H A Dsdma_v6_0.c387 rb_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL));
389 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl);
486 rb_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL));
494 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl);
581 WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl);
/openbsd-current/sys/dev/pci/drm/amd/include/asic_reg/gc/
H A Dgc_11_0_0_offset.h190 #define regSDMA0_QUEUE0_RB_CNTL 0x0080 macro
[all...]
H A Dgc_11_0_3_offset.h196 #define regSDMA0_QUEUE0_RB_CNTL 0x0080 macro
[all...]

Completed in 446 milliseconds