Searched refs:regPHYPLLF_PIXCLK_RESYNC_CNTL_BASE_IDX (Results 1 - 2 of 2) sorted by relevance

/openbsd-current/sys/dev/pci/drm/amd/display/dc/dcn31/
H A Ddcn31_resource.h69 #define regPHYPLLF_PIXCLK_RESYNC_CNTL_BASE_IDX 1 macro
/openbsd-current/sys/dev/pci/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_1_6_offset.h520 #define regPHYPLLF_PIXCLK_RESYNC_CNTL_BASE_IDX 1 macro
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