Searched refs:regMC_VM_CACHEABLE_DRAM_CNTL (Results 1 - 4 of 4) sorted by relevance

/openbsd-current/sys/dev/pci/drm/amd/include/asic_reg/mmhub/
H A Dmmhub_1_8_0_offset.h3114 #define regMC_VM_CACHEABLE_DRAM_CNTL 0x0c99 macro
H A Dmmhub_1_7_offset.h5100 #define regMC_VM_CACHEABLE_DRAM_CNTL 0x0cba macro
/openbsd-current/sys/dev/pci/drm/amd/include/asic_reg/gc/
H A Dgc_9_4_2_offset.h7366 #define regMC_VM_CACHEABLE_DRAM_CNTL 0x097a macro
H A Dgc_9_4_3_offset.h2048 #define regMC_VM_CACHEABLE_DRAM_CNTL 0x0959 macro

Completed in 436 milliseconds