Searched refs:regGFX_IMU_C2PMSG_ACCESS_CTRL0 (Results 1 - 3 of 3) sorted by relevance

/openbsd-current/sys/dev/pci/drm/amd/amdgpu/
H A Dimu_v11_0.c146 WREG32_SOC15(GC, 0, regGFX_IMU_C2PMSG_ACCESS_CTRL0, 0xffffff);
/openbsd-current/sys/dev/pci/drm/amd/include/asic_reg/gc/
H A Dgc_11_0_0_offset.h11050 #define regGFX_IMU_C2PMSG_ACCESS_CTRL0 macro
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H A Dgc_11_0_3_offset.h11462 #define regGFX_IMU_C2PMSG_ACCESS_CTRL0 macro
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