Searched refs:regCP_GFX_CNTL (Results 1 - 3 of 3) sorted by relevance

/openbsd-current/sys/dev/pci/drm/amd/amdgpu/
H A Dgfx_v11_0.c4200 tmp = RREG32_SOC15(GC, 0, regCP_GFX_CNTL);
4202 WREG32_SOC15(GC, 0, regCP_GFX_CNTL, tmp);
/openbsd-current/sys/dev/pci/drm/amd/include/asic_reg/gc/
H A Dgc_11_0_0_offset.h7976 #define regCP_GFX_CNTL 0x2a00 macro
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H A Dgc_11_0_3_offset.h8290 #define regCP_GFX_CNTL 0x2a00 macro
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