/openbsd-current/sys/dev/pci/drm/amd/display/amdgpu_dm/ |
H A D | amdgpu_dm_pp_smu.c | 122 clks->num_levels = 6; 127 clks->num_levels = 6; 132 clks->num_levels = 2; 137 clks->num_levels = 0; 224 dc_clks->num_levels = DM_PP_MAX_CLOCK_LEVELS; 226 dc_clks->num_levels = pp_clks->count; 231 for (i = 0; i < dc_clks->num_levels; i++) { 244 if (pp_clks->num_levels > DM_PP_MAX_CLOCK_LEVELS) { 247 pp_clks->num_levels, 250 clk_level_info->num_levels [all...] |
/openbsd-current/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/ |
H A D | dcn30_clk_mgr.c | 80 static void dcn3_init_single_clock(struct clk_mgr_internal *clk_mgr, uint32_t clk, unsigned int *entry_0, unsigned int *num_levels) argument 88 *num_levels = 2; 91 /* will set num_levels to 0 on failure */ 92 *num_levels = ret & 0xFF; 94 /* if the initial message failed, num_levels will be 0 */ 95 for (i = 0; i < *num_levels; i++) { 111 unsigned int num_levels; local 134 &num_levels); 140 &num_levels); 145 &num_levels); 409 unsigned int num_levels; local [all...] |
/openbsd-current/sys/dev/pci/drm/amd/display/dc/dce120/ |
H A D | dce120_resource.c | 929 &eng_clks) || eng_clks.num_levels == 0) { 931 eng_clks.num_levels = 8; 934 for (i = 0; i < eng_clks.num_levels; i++) { 942 eng_clks.data[eng_clks.num_levels-1].clocks_in_khz, 1000); 944 eng_clks.data[eng_clks.num_levels/8].clocks_in_khz, 1000); 946 eng_clks.data[eng_clks.num_levels*2/8].clocks_in_khz, 1000); 948 eng_clks.data[eng_clks.num_levels*3/8].clocks_in_khz, 1000); 950 eng_clks.data[eng_clks.num_levels*4/8].clocks_in_khz, 1000); 952 eng_clks.data[eng_clks.num_levels*5/8].clocks_in_khz, 1000); 954 eng_clks.data[eng_clks.num_levels* [all...] |
/openbsd-current/sys/dev/pci/drm/amd/display/dc/dce112/ |
H A D | dce112_resource.c | 1090 clks.clocks_in_khz[clks.num_levels-1], 1000); 1092 clks.clocks_in_khz[clks.num_levels/8], 1000); 1094 clks.clocks_in_khz[clks.num_levels*2/8], 1000); 1096 clks.clocks_in_khz[clks.num_levels*3/8], 1000); 1098 clks.clocks_in_khz[clks.num_levels*4/8], 1000); 1100 clks.clocks_in_khz[clks.num_levels*5/8], 1000); 1102 clks.clocks_in_khz[clks.num_levels*6/8], 1000); 1115 clks.clocks_in_khz[clks.num_levels>>1] * memory_type_multiplier, 1118 clks.clocks_in_khz[clks.num_levels-1] * memory_type_multiplier, 1126 eng_clks.data[eng_clks.num_levels [all...] |
/openbsd-current/sys/dev/pci/drm/amd/display/dc/ |
H A D | dm_services_types.h | 98 uint32_t num_levels; member in struct:dm_pp_clock_levels 108 uint32_t num_levels; member in struct:dm_pp_clock_levels_with_latency 118 uint32_t num_levels; member in struct:dm_pp_clock_levels_with_voltage
|
/openbsd-current/sys/dev/pci/drm/amd/include/ |
H A D | dm_pp_interface.h | 175 uint32_t num_levels; member in struct:pp_clock_levels_with_latency 185 uint32_t num_levels; member in struct:pp_clock_levels_with_voltage
|
/openbsd-current/sys/dev/pci/drm/radeon/ |
H A D | r100_track.h | 44 unsigned num_levels; member in struct:r100_cs_track_texture
|
H A D | sumo_dpm.c | 347 u32 highest_engine_clock = ps->levels[ps->num_levels - 1].sclk; 354 for (i = 0; i < ps->num_levels - 1; i++) 408 for (i = 0; i < ps->num_levels; i++) { 409 asi = (i == ps->num_levels - 1) ? pi->pasi : pi->asi; 423 a_t = CG_R(m_a * r[ps->num_levels - 1] / 100) | 424 CG_L(m_a * l[ps->num_levels - 1] / 100); 670 pi->boost_pl = new_ps->levels[new_ps->num_levels - 1]; 743 dpm_ctrl4 |= (1 << (new_ps->num_levels - 1)); 759 u32 n_current_state_levels = (old_ps == NULL) ? 1 : old_ps->num_levels; 761 for (i = 0; i < new_ps->num_levels; [all...] |
H A D | trinity_dpm.h | 48 u32 num_levels; member in struct:trinity_ps
|
H A D | trinity_dpm.c | 802 u32 n_current_state_levels = (old_ps == NULL) ? 1 : old_ps->num_levels; 804 for (i = 0; i < new_ps->num_levels; i++) { 809 for (i = new_ps->num_levels; i < n_current_state_levels; i++) 925 if (new_ps->levels[new_ps->num_levels - 1].sclk >= 926 current_ps->levels[current_ps->num_levels - 1].sclk) 939 if (new_ps->levels[new_ps->num_levels - 1].sclk < 940 current_ps->levels[current_ps->num_levels - 1].sclk) 1165 if (ps->num_levels <= 1) 1172 ret = trinity_dpm_n_levels_disabled(rdev, ps->num_levels - 1); 1176 for (i = 0; i < ps->num_levels; [all...] |
H A D | kv_dpm.h | 83 u32 num_levels; member in struct:kv_ps
|
H A D | sumo_dpm.h | 47 u32 num_levels; member in struct:sumo_ps
|
/openbsd-current/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/ |
H A D | dcn32_clk_mgr.c | 126 unsigned int *num_levels) 135 *num_levels = 2; 138 /* will set num_levels to 0 on failure */ 139 *num_levels = ret & 0xFF; 141 /* if the initial message failed, num_levels will be 0 */ 142 for (i = 0; i < *num_levels; i++) { 158 unsigned int num_levels; local 206 num_levels = num_entries_per_clk->num_dispclk_levels; 218 for (i = 0; i < num_levels; i++) 224 for (i = 0; i < num_levels; 125 dcn32_init_single_clock(struct clk_mgr_internal *clk_mgr, PPCLK_e clk, unsigned int *entry_0, unsigned int *num_levels) argument 842 unsigned int num_levels; local [all...] |
/openbsd-current/sys/dev/pci/drm/i915/display/ |
H A D | intel_wm.c | 151 for (level = 0; level < dev_priv->display.wm.num_levels; level++) { 191 for (level = 0; level < dev_priv->display.wm.num_levels; level++) { 311 if (ret != dev_priv->display.wm.num_levels) 316 for (level = 0; level < dev_priv->display.wm.num_levels; level++)
|
H A D | i9xx_wm.c | 828 dev_priv->display.wm.num_levels = G4X_WM_LEVEL_HPLL + 1; 935 for (; level < dev_priv->display.wm.num_levels; level++) { 954 for (; level < dev_priv->display.wm.num_levels; level++) { 984 for (level = 0; level < dev_priv->display.wm.num_levels; level++) { 1054 if (level >= dev_priv->display.wm.num_levels) 1390 dev_priv->display.wm.num_levels = VLV_WM_LEVEL_PM2 + 1; 1396 dev_priv->display.wm.num_levels = VLV_WM_LEVEL_DDR_DVFS + 1; 1532 for (; level < dev_priv->display.wm.num_levels; level++) { 1561 for (; level < dev_priv->display.wm.num_levels; level++) { 1585 for (level = 0; level < dev_priv->display.wm.num_levels; leve 2960 int level, num_levels = dev_priv->display.wm.num_levels; local [all...] |
H A D | skl_watermark.c | 364 for (level = i915->display.wm.num_levels - 1; 752 for (level = 0; level < i915->display.wm.num_levels; level++) { 1528 for (level = i915->display.wm.num_levels - 1; level >= 0; level--) { 1604 for (level++; level < i915->display.wm.num_levels; level++) { 1993 for (level = 0; level < i915->display.wm.num_levels; level++) { 2245 for (level = i915->display.wm.num_levels - 1; level >= 0; level--) { 2283 crtc_state->wm_level_disabled = level < i915->display.wm.num_levels - 1; 2285 for (level++; level < i915->display.wm.num_levels; level++) { 2392 for (level = 0; level < i915->display.wm.num_levels; level++) 2427 for (level = 0; level < i915->display.wm.num_levels; leve 3295 adjust_wm_latency(struct drm_i915_private *i915, u16 wm[], int num_levels, int read_latency) argument 3340 int num_levels = i915->display.wm.num_levels; local 3360 int num_levels = i915->display.wm.num_levels; local [all...] |
H A D | intel_display_core.h | 257 u8 num_levels; member in struct:intel_wm
|
/openbsd-current/sys/dev/pci/drm/amd/display/dc/clk_mgr/dce110/ |
H A D | dce110_clk_mgr.c | 76 if (dc->sclk_lvls.num_levels == 0) 79 for (i = 0; i < dc->sclk_lvls.num_levels; i++) { 89 return dc->sclk_lvls.clocks_in_khz[dc->sclk_lvls.num_levels - 1];
|
/openbsd-current/sys/dev/pci/drm/amd/display/dc/dce110/ |
H A D | dce110_resource.c | 1294 clks.clocks_in_khz[clks.num_levels-1], 1000); 1296 clks.clocks_in_khz[clks.num_levels/8], 1000); 1298 clks.clocks_in_khz[clks.num_levels*2/8], 1000); 1300 clks.clocks_in_khz[clks.num_levels*3/8], 1000); 1302 clks.clocks_in_khz[clks.num_levels*4/8], 1000); 1304 clks.clocks_in_khz[clks.num_levels*5/8], 1000); 1306 clks.clocks_in_khz[clks.num_levels*6/8], 1000); 1317 clks.clocks_in_khz[clks.num_levels-1], 1000); 1319 clks.clocks_in_khz[clks.num_levels>>1], 1000); 1332 clks.clocks_in_khz[clks.num_levels>> [all...] |
/openbsd-current/sys/dev/pci/drm/amd/pm/legacy-dpm/ |
H A D | kv_dpm.h | 109 u32 num_levels; member in struct:kv_ps
|
/openbsd-current/sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ |
H A D | smu10_hwmgr.c | 1203 clocks->num_levels = 0; 1206 clocks->data[clocks->num_levels].clocks_in_khz = 1208 clocks->data[clocks->num_levels].latency_in_us = latency_required ? 1212 clocks->num_levels++; 1257 clocks->num_levels = 0; 1260 clocks->data[clocks->num_levels].clocks_in_khz = pclk_vol_table->entries[i].clk * 10; 1261 clocks->data[clocks->num_levels].voltage_in_mv = pclk_vol_table->entries[i].vol; 1262 clocks->num_levels++;
|
/openbsd-current/sys/dev/pci/drm/amd/pm/swsmu/smu13/ |
H A D | aldebaran_ppt.c | 562 clocks->num_levels = min_t(uint32_t, 566 for (i = 0; i < clocks->num_levels; i++) { 784 display_levels = (clocks.num_levels == 1) ? 1 : 2; 828 for (i = 0; i < clocks.num_levels; i++) 831 (clocks.num_levels == 1) ? "*" : 851 for (i = 0; i < clocks.num_levels; i++) 854 (clocks.num_levels == 1) ? "*" : 877 (clocks.num_levels == 1) ? "*" : 900 (clocks.num_levels == 1) ? "*" : 923 (clocks.num_levels [all...] |
/openbsd-current/gnu/llvm/lldb/source/Interpreter/ |
H A D | Options.cpp | 109 int num_levels = GetRequiredOptions().size(); local 110 if (num_levels) { 111 for (int i = 0; i < num_levels && !options_are_valid; ++i) { 570 int num_levels = GetRequiredOptions().size(); 571 if (num_levels) { 572 for (int i = 0; i < num_levels && !options_are_valid; ++i) {
|
/openbsd-current/sys/dev/pci/drm/amd/display/dc/dml/calcs/ |
H A D | dcn_calcs.c | 1453 ASSERT(fclks->num_levels); 1456 vmid0p72_idx = fclks->num_levels - 1457 (fclks->num_levels > 2 ? 3 : (fclks->num_levels > 1 ? 2 : 1)); 1458 vnom0p8_idx = fclks->num_levels - (fclks->num_levels > 1 ? 2 : 1); 1459 vmax0p9_idx = fclks->num_levels - 1; 1481 if (dcfclks->num_levels >= 3) { 1483 dc->dcn_soc->dcfclkv_mid0p72 = dcfclks->data[dcfclks->num_levels - 3].clocks_in_khz / 1000.0; 1484 dc->dcn_soc->dcfclkv_nom0p8 = dcfclks->data[dcfclks->num_levels [all...] |
/openbsd-current/sys/dev/pci/drm/amd/pm/swsmu/smu11/ |
H A D | arcturus_ppt.c | 578 clocks->num_levels = min_t(uint32_t, 582 for (i = 0; i < clocks->num_levels; i++) { 799 for (i = 0; i < clocks.num_levels; i++) 802 (clocks.num_levels == 1) ? "*" : 822 for (i = 0; i < clocks.num_levels; i++) 825 (clocks.num_levels == 1) ? "*" : 845 for (i = 0; i < clocks.num_levels; i++) 848 (clocks.num_levels == 1) ? "*" : 871 (clocks.num_levels == 1) ? "*" : 894 (clocks.num_levels [all...] |