Searched refs:mmVGT_ESGS_RING_SIZE (Results 1 - 8 of 8) sorted by relevance

/openbsd-current/sys/dev/pci/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_d.h1664 #define mmVGT_ESGS_RING_SIZE 0x2232 macro
H A Dgfx_7_0_d.h2386 #define mmVGT_ESGS_RING_SIZE 0xc240 macro
H A Dgfx_7_2_d.h2411 #define mmVGT_ESGS_RING_SIZE 0xc240 macro
H A Dgfx_8_0_d.h2651 #define mmVGT_ESGS_RING_SIZE 0xc240 macro
H A Dgfx_8_1_d.h2630 #define mmVGT_ESGS_RING_SIZE 0xc240 macro
/openbsd-current/sys/dev/pci/drm/amd/amdgpu/
H A Dgfx_v10_0.c6913 * has been remapped to mmVGT_ESGS_RING_SIZE
6936 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE);
6937 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, 0);
6940 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE) == pattern) {
6944 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, data);
7005 /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */
7060 /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */
7063 (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE) <<
/openbsd-current/sys/dev/pci/drm/amd/include/asic_reg/gc/
H A Dgc_10_3_0_offset.h2362 #define mmVGT_ESGS_RING_SIZE 0x0fc1 macro
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H A Dgc_10_1_0_offset.h2287 #define mmVGT_ESGS_RING_SIZE 0x0fd2 macro
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