Searched refs:mmUVD_VCPU_NONCACHE_OFFSET0 (Results 1 - 6 of 6) sorted by relevance

/openbsd-current/sys/dev/pci/drm/amd/amdgpu/
H A Dvcn_v2_0.c380 WREG32_SOC15(UVD, 0, mmUVD_VCPU_NONCACHE_OFFSET0, 0);
473 UVD, 0, mmUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect);
H A Dvcn_v3_0.c493 WREG32_SOC15(VCN, inst, mmUVD_VCPU_NONCACHE_OFFSET0, 0);
584 VCN, inst_idx, mmUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect);
H A Dvcn_v2_5.c463 WREG32_SOC15(VCN, i, mmUVD_VCPU_NONCACHE_OFFSET0, 0);
555 VCN, 0, mmUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect);
/openbsd-current/sys/dev/pci/drm/amd/include/asic_reg/vcn/
H A Dvcn_2_0_0_offset.h650 #define mmUVD_VCPU_NONCACHE_OFFSET0 0x0254 macro
H A Dvcn_2_5_offset.h721 #define mmUVD_VCPU_NONCACHE_OFFSET0 0x0152 macro
H A Dvcn_3_0_0_offset.h1097 #define mmUVD_VCPU_NONCACHE_OFFSET0 0x0152 macro

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