Searched refs:mmSQ_EDC_SEC_CNT (Results 1 - 8 of 8) sorted by relevance

/openbsd-current/sys/dev/pci/drm/amd/include/asic_reg/gc/
H A Dgc_9_4_1_offset.h162 #define mmSQ_EDC_SEC_CNT 0x03a3 macro
H A Dgc_9_1_offset.h557 #define mmSQ_EDC_SEC_CNT 0x03a3 macro
H A Dgc_9_0_offset.h563 #define mmSQ_EDC_SEC_CNT 0x03a3 macro
/openbsd-current/sys/dev/pci/drm/amd/amdgpu/
H A Dgfx_v9_4.c63 { SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_SEC_CNT), 0, 8, 16 },
H A Dgfx_v8_0.c1481 mmSQ_EDC_SEC_CNT,
H A Dgfx_v9_0.c4276 { SOC15_REG_ENTRY(GC, 0, mmSQ_EDC_SEC_CNT), 0, 4, 16},
/openbsd-current/sys/dev/pci/drm/amd/include/asic_reg/gca/
H A Dgfx_8_0_d.h2097 #define mmSQ_EDC_SEC_CNT 0x23a1 macro
H A Dgfx_8_1_d.h2065 #define mmSQ_EDC_SEC_CNT 0x23a1 macro

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