Searched refs:mmSDMA3_RLC5_MIDCMD_DATA0 (Results 1 - 2 of 2) sorted by relevance

/openbsd-current/sys/dev/pci/drm/amd/include/asic_reg/sdma3/
H A Dsdma3_4_2_2_offset.h854 #define mmSDMA3_RLC5_MIDCMD_DATA0 0x0328 macro
/openbsd-current/sys/dev/pci/drm/amd/include/asic_reg/gc/
H A Dgc_10_3_0_offset.h12467 #define mmSDMA3_RLC5_MIDCMD_DATA0 macro
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