Searched refs:mmSDMA0_UTCL1_CNTL (Results 1 - 8 of 8) sorted by relevance
| /openbsd-current/sys/dev/pci/drm/amd/include/asic_reg/sdma0/ |
| H A D | sdma0_4_1_offset.h | 132 #define mmSDMA0_UTCL1_CNTL 0x003c macro
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| H A D | sdma0_4_0_offset.h | 134 #define mmSDMA0_UTCL1_CNTL 0x003c macro
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| H A D | sdma0_4_2_2_offset.h | 134 #define mmSDMA0_UTCL1_CNTL 0x003c macro
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| H A D | sdma0_4_2_offset.h | 134 #define mmSDMA0_UTCL1_CNTL 0x003c macro
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| /openbsd-current/sys/dev/pci/drm/amd/amdgpu/ |
| H A D | sdma_v5_0.c | 788 temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL));
791 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL), temp);
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| H A D | sdma_v5_2.c | 592 temp = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL));
595 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL), temp);
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| /openbsd-current/sys/dev/pci/drm/amd/include/asic_reg/gc/ |
| H A D | gc_10_3_0_offset.h | 108 #define mmSDMA0_UTCL1_CNTL 0x003c macro
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| H A D | gc_10_1_0_offset.h | 109 #define mmSDMA0_UTCL1_CNTL 0x003c macro
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