Searched refs:mmSDMA0_RLC3_RB_WPTR_POLL_CNTL (Results 1 - 6 of 6) sorted by relevance
| /openbsd-current/sys/dev/pci/drm/amd/amdgpu/ |
| H A D | sdma_v5_0.c | 74 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
100 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
118 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0x0000fff0, 0x00403000),
123 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
128 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
145 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
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| H A D | sdma_v4_0.c | 173 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC3_RB_WPTR_POLL_CNTL, 0xfffffff7, 0x00403000),
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| /openbsd-current/sys/dev/pci/drm/amd/include/asic_reg/sdma0/ |
| H A D | sdma0_4_2_2_offset.h | 644 #define mmSDMA0_RLC3_RB_WPTR_POLL_CNTL 0x023f macro
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| H A D | sdma0_4_2_offset.h | 640 #define mmSDMA0_RLC3_RB_WPTR_POLL_CNTL 0x0267 macro
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| /openbsd-current/sys/dev/pci/drm/amd/include/asic_reg/gc/ |
| H A D | gc_10_3_0_offset.h | 646 #define mmSDMA0_RLC3_RB_WPTR_POLL_CNTL 0x023f macro
[all...] |
| H A D | gc_10_1_0_offset.h | 633 #define mmSDMA0_RLC3_RB_WPTR_POLL_CNTL 0x0267 macro
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