Searched refs:mmSDMA0_RLC1_RB_WPTR (Results 1 - 10 of 10) sorted by relevance

/openbsd-current/sys/dev/pci/drm/amd/include/asic_reg/sdma0/
H A Dsdma0_4_1_offset.h384 #define mmSDMA0_RLC1_RB_WPTR 0x01a5 macro
H A Dsdma0_4_0_offset.h472 #define mmSDMA0_RLC1_RB_WPTR 0x01a5 macro
H A Dsdma0_4_2_2_offset.h472 #define mmSDMA0_RLC1_RB_WPTR 0x018d macro
H A Dsdma0_4_2_offset.h468 #define mmSDMA0_RLC1_RB_WPTR 0x01a5 macro
/openbsd-current/sys/dev/pci/drm/amd/include/asic_reg/oss/
H A Doss_2_4_d.h246 #define mmSDMA0_RLC1_RB_WPTR 0x3584 macro
H A Doss_2_0_d.h295 #define mmSDMA0_RLC1_RB_WPTR 0x3584 macro
H A Doss_3_0_1_d.h295 #define mmSDMA0_RLC1_RB_WPTR 0x3584 macro
H A Doss_3_0_d.h414 #define mmSDMA0_RLC1_RB_WPTR 0x3584 macro
/openbsd-current/sys/dev/pci/drm/amd/include/asic_reg/gc/
H A Dgc_10_3_0_offset.h466 #define mmSDMA0_RLC1_RB_WPTR 0x018d macro
[all...]
H A Dgc_10_1_0_offset.h463 #define mmSDMA0_RLC1_RB_WPTR 0x01a5 macro
[all...]

Completed in 425 milliseconds