Searched refs:mmSDMA0_RLC1_IB_CNTL (Results 1 - 13 of 13) sorted by relevance
| /openbsd-current/sys/dev/pci/drm/amd/amdgpu/ |
| H A D | sdma_v3_0.c | 86 mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
105 mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
124 mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
138 mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
153 mmSDMA0_RLC1_IB_CNTL, 0x00000100, 0x00000100,
173 mmSDMA0_RLC1_IB_CNTL, 0x00000100, 0x00000100,
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| H A D | mxgpu_vi.c | 110 mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
249 mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
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| H A D | sdma_v4_0.c | 99 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_IB_CNTL, 0x800f0100, 0x00000100),
145 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100),
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| /openbsd-current/sys/dev/pci/drm/amd/include/asic_reg/sdma0/ |
| H A D | sdma0_4_1_offset.h | 394 #define mmSDMA0_RLC1_IB_CNTL 0x01aa macro
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| H A D | sdma0_4_0_offset.h | 482 #define mmSDMA0_RLC1_IB_CNTL 0x01aa macro
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| H A D | sdma0_4_2_2_offset.h | 482 #define mmSDMA0_RLC1_IB_CNTL 0x0192 macro
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| H A D | sdma0_4_2_offset.h | 478 #define mmSDMA0_RLC1_IB_CNTL 0x01aa macro
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| /openbsd-current/sys/dev/pci/drm/amd/include/asic_reg/oss/ |
| H A D | oss_2_4_d.h | 252 #define mmSDMA0_RLC1_IB_CNTL 0x358a macro
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| H A D | oss_2_0_d.h | 301 #define mmSDMA0_RLC1_IB_CNTL 0x358a macro
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| H A D | oss_3_0_1_d.h | 301 #define mmSDMA0_RLC1_IB_CNTL 0x358a macro
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| H A D | oss_3_0_d.h | 420 #define mmSDMA0_RLC1_IB_CNTL 0x358a macro
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| /openbsd-current/sys/dev/pci/drm/amd/include/asic_reg/gc/ |
| H A D | gc_10_3_0_offset.h | 476 #define mmSDMA0_RLC1_IB_CNTL 0x0192 macro
[all...] |
| H A D | gc_10_1_0_offset.h | 473 #define mmSDMA0_RLC1_IB_CNTL 0x01aa macro
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