Searched refs:mmSDMA0_RLC0_RB_BASE (Results 1 - 16 of 16) sorted by relevance

/openbsd-current/sys/dev/pci/drm/amd/include/asic_reg/sdma0/
H A Dsdma0_4_1_offset.h292 #define mmSDMA0_RLC0_RB_BASE 0x0141 macro
H A Dsdma0_4_0_offset.h380 #define mmSDMA0_RLC0_RB_BASE 0x0141 macro
H A Dsdma0_4_2_2_offset.h380 #define mmSDMA0_RLC0_RB_BASE 0x0131 macro
H A Dsdma0_4_2_offset.h376 #define mmSDMA0_RLC0_RB_BASE 0x0141 macro
/openbsd-current/sys/dev/pci/drm/amd/amdgpu/
H A Damdgpu_amdkfd_arcturus.c178 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_BASE, m->sdmax_rlcx_rb_base);
H A Damdgpu_amdkfd_gfx_v7.c279 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_BASE, m->sdma_rlc_rb_base);
H A Damdgpu_amdkfd_gfx_v10_3.c413 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_BASE, m->sdmax_rlcx_rb_base);
H A Damdgpu_amdkfd_gfx_v8.c302 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_BASE, m->sdmax_rlcx_rb_base);
H A Damdgpu_amdkfd_gfx_v10.c427 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_BASE, m->sdmax_rlcx_rb_base);
H A Damdgpu_amdkfd_gfx_v9.c440 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_BASE, m->sdmax_rlcx_rb_base);
/openbsd-current/sys/dev/pci/drm/amd/include/asic_reg/oss/
H A Doss_2_4_d.h215 #define mmSDMA0_RLC0_RB_BASE 0x3501 macro
H A Doss_2_0_d.h269 #define mmSDMA0_RLC0_RB_BASE 0x3501 macro
H A Doss_3_0_1_d.h254 #define mmSDMA0_RLC0_RB_BASE 0x3501 macro
H A Doss_3_0_d.h376 #define mmSDMA0_RLC0_RB_BASE 0x3501 macro
/openbsd-current/sys/dev/pci/drm/amd/include/asic_reg/gc/
H A Dgc_10_3_0_offset.h370 #define mmSDMA0_RLC0_RB_BASE 0x0131 macro
[all...]
H A Dgc_10_1_0_offset.h372 #define mmSDMA0_RLC0_RB_BASE 0x0141 macro
[all...]

Completed in 629 milliseconds