Searched refs:mmSDMA0_POWER_CNTL (Results 1 - 15 of 15) sorted by relevance
/openbsd-current/sys/dev/pci/drm/amd/amdgpu/ |
H A D | amdgpu_cik_sdma.c | 903 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET); 906 WREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data); 908 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET); 911 WREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data); 913 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET); 916 WREG32(mmSDMA0_POWER_CNTL + SDMA0_REGISTER_OFFSET, data); 918 orig = data = RREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET); 921 WREG32(mmSDMA0_POWER_CNTL + SDMA1_REGISTER_OFFSET, data);
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H A D | sdma_v3_0.c | 151 mmSDMA0_POWER_CNTL, 0x00000800, 0x0003c800, 171 mmSDMA0_POWER_CNTL, 0x00000800, 0x0003c800, 1478 temp = data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i]); 1482 WREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i], data); 1486 temp = data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i]); 1490 WREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i], data); 1538 data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[0]);
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H A D | sdma_v4_0.c | 96 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0x003ff006, 0x0003c000), 142 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0xfc3fffff, 0x40000051), 288 SOC15_REG_GOLDEN_VALUE(SDMA0, 0, mmSDMA0_POWER_CNTL, 0x003fff07, 0x40000051), 1231 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL)); 1234 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data); 1243 def = data = RREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL)); 1250 WREG32(SOC15_REG_OFFSET(SDMA0, 0, mmSDMA0_POWER_CNTL), data); 2229 def = data = RREG32_SDMA(0, mmSDMA0_POWER_CNTL); 2232 WREG32_SDMA(0, mmSDMA0_POWER_CNTL, data); 2237 def = data = RREG32_SDMA(0, mmSDMA0_POWER_CNTL); [all...] |
H A D | sdma_v5_0.c | 1676 def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL)); 1679 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data); 1683 def = data = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL)); 1686 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data); 1736 data = RREG32(sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_POWER_CNTL));
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H A D | sdma_v5_2.c | 1588 def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL)); 1591 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data); 1595 def = data = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL)); 1598 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_POWER_CNTL), data); 1653 data = RREG32_KIQ(sdma_v5_2_get_reg_offset(adev, 0, mmSDMA0_POWER_CNTL));
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/openbsd-current/sys/dev/pci/drm/amd/include/asic_reg/sdma0/ |
H A D | sdma0_4_1_offset.h | 64 #define mmSDMA0_POWER_CNTL 0x001a macro
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H A D | sdma0_4_0_offset.h | 66 #define mmSDMA0_POWER_CNTL 0x001a macro
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H A D | sdma0_4_2_2_offset.h | 66 #define mmSDMA0_POWER_CNTL 0x001a macro
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H A D | sdma0_4_2_offset.h | 66 #define mmSDMA0_POWER_CNTL 0x001a macro
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/openbsd-current/sys/dev/pci/drm/amd/include/asic_reg/oss/ |
H A D | oss_2_4_d.h | 159 #define mmSDMA0_POWER_CNTL 0x3402 macro
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H A D | oss_2_0_d.h | 221 #define mmSDMA0_POWER_CNTL 0x3402 macro
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H A D | oss_3_0_1_d.h | 156 #define mmSDMA0_POWER_CNTL 0x3402 macro
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H A D | oss_3_0_d.h | 293 #define mmSDMA0_POWER_CNTL 0x3402 macro
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/openbsd-current/sys/dev/pci/drm/amd/include/asic_reg/gc/ |
H A D | gc_10_3_0_offset.h | 48 #define mmSDMA0_POWER_CNTL 0x001a macro [all...] |
H A D | gc_10_1_0_offset.h | 41 #define mmSDMA0_POWER_CNTL 0x001a macro [all...] |
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