Searched refs:mmSDMA0_GFX_RB_WPTR_HI (Results 1 - 9 of 9) sorted by relevance
/openbsd-current/sys/dev/pci/drm/amd/include/asic_reg/sdma0/ |
H A D | sdma0_4_1_offset.h | 216 #define mmSDMA0_GFX_RB_WPTR_HI 0x0086 macro
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H A D | sdma0_4_0_offset.h | 220 #define mmSDMA0_GFX_RB_WPTR_HI 0x0086 macro
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H A D | sdma0_4_2_2_offset.h | 220 #define mmSDMA0_GFX_RB_WPTR_HI 0x0086 macro
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H A D | sdma0_4_2_offset.h | 216 #define mmSDMA0_GFX_RB_WPTR_HI 0x0086 macro
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/openbsd-current/sys/dev/pci/drm/amd/amdgpu/ |
H A D | sdma_v5_0.c | 316 wptr = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI)); 393 ring->me, mmSDMA0_GFX_RB_WPTR_HI), 713 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0); 750 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI),
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H A D | sdma_v5_2.c | 156 wptr = RREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI)); 201 WREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI), 520 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0); 554 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr << 2));
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H A D | sdma_v4_0.c | 632 wptr = RREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR_HI); 679 WREG32_SDMA(ring->me, mmSDMA0_GFX_RB_WPTR_HI, 1059 WREG32_SDMA(i, mmSDMA0_GFX_RB_WPTR_HI, 0);
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/openbsd-current/sys/dev/pci/drm/amd/include/asic_reg/gc/ |
H A D | gc_10_3_0_offset.h | 202 #define mmSDMA0_GFX_RB_WPTR_HI 0x0086 macro [all...] |
H A D | gc_10_1_0_offset.h | 214 #define mmSDMA0_GFX_RB_WPTR_HI 0x0086 macro [all...] |
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