Searched refs:mmSDMA0_GFX_RB_RPTR (Results 1 - 14 of 14) sorted by relevance

/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/sdma0/
H A Dsdma0_4_1_offset.h212 #define mmSDMA0_GFX_RB_RPTR 0x0083 macro
H A Dsdma0_4_0_offset.h216 #define mmSDMA0_GFX_RB_RPTR 0x0083 macro
H A Dsdma0_4_2_2_offset.h216 #define mmSDMA0_GFX_RB_RPTR 0x0083 macro
H A Dsdma0_4_2_offset.h212 #define mmSDMA0_GFX_RB_RPTR 0x0083 macro
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/oss/
H A Doss_2_4_d.h192 #define mmSDMA0_GFX_RB_RPTR 0x3483 macro
H A Doss_2_0_d.h251 #define mmSDMA0_GFX_RB_RPTR 0x3483 macro
H A Doss_3_0_1_d.h219 #define mmSDMA0_GFX_RB_RPTR 0x3483 macro
H A Doss_3_0_d.h344 #define mmSDMA0_GFX_RB_RPTR 0x3483 macro
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
H A Damdgpu_sdma_v2_4.c455 WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0);
H A Damdgpu_cik_sdma.c476 WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0);
H A Damdgpu_sdma_v3_0.c694 WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0);
H A Damdgpu_sdma_v5_0.c647 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0);
H A Damdgpu_sdma_v4_0.c1106 WREG32_SDMA(i, mmSDMA0_GFX_RB_RPTR, 0);
/netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/
H A Dgc_10_1_0_offset.h207 #define mmSDMA0_GFX_RB_RPTR 0x0083 macro
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