Searched refs:mmSDMA0_GFX_RB_BASE_HI (Results 1 - 16 of 16) sorted by relevance
| /openbsd-current/sys/dev/pci/drm/amd/include/asic_reg/sdma0/ |
| H A D | sdma0_4_1_offset.h | 208 #define mmSDMA0_GFX_RB_BASE_HI 0x0082 macro
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| H A D | sdma0_4_0_offset.h | 212 #define mmSDMA0_GFX_RB_BASE_HI 0x0082 macro
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| H A D | sdma0_4_2_2_offset.h | 212 #define mmSDMA0_GFX_RB_BASE_HI 0x0082 macro
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| H A D | sdma0_4_2_offset.h | 208 #define mmSDMA0_GFX_RB_BASE_HI 0x0082 macro
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| /openbsd-current/sys/dev/pci/drm/amd/include/asic_reg/oss/ |
| H A D | oss_2_4_d.h | 189 #define mmSDMA0_GFX_RB_BASE_HI 0x3482 macro
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| H A D | oss_2_0_d.h | 248 #define mmSDMA0_GFX_RB_BASE_HI 0x3482 macro
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| H A D | oss_3_0_1_d.h | 216 #define mmSDMA0_GFX_RB_BASE_HI 0x3482 macro
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| H A D | oss_3_0_d.h | 341 #define mmSDMA0_GFX_RB_BASE_HI 0x3482 macro
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| /openbsd-current/sys/dev/pci/drm/amd/amdgpu/ |
| H A D | amdgpu_cik_sdma.c | 477 WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40);
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| H A D | sdma_v2_4.c | 453 WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40);
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| H A D | sdma_v3_0.c | 692 WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40);
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| H A D | sdma_v5_0.c | 739 WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE_HI),
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| H A D | sdma_v5_2.c | 545 WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE_HI), ring->gpu_addr >> 40);
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| H A D | sdma_v4_0.c | 1071 WREG32_SDMA(i, mmSDMA0_GFX_RB_BASE_HI, ring->gpu_addr >> 40);
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| /openbsd-current/sys/dev/pci/drm/amd/include/asic_reg/gc/ |
| H A D | gc_10_3_0_offset.h | 194 #define mmSDMA0_GFX_RB_BASE_HI 0x0082 macro
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| H A D | gc_10_1_0_offset.h | 206 #define mmSDMA0_GFX_RB_BASE_HI 0x0082 macro
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