Searched refs:mmSDMA0_F32_CNTL (Results 1 - 16 of 16) sorted by relevance
| /openbsd-current/sys/dev/pci/drm/amd/amdgpu/ |
| H A D | amdgpu_cik_sdma.c | 409 me_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]);
414 WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], me_cntl);
1071 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET);
1073 WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp);
1077 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET);
1079 WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp);
|
| H A D | sdma_v2_4.c | 385 f32_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]);
390 WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], f32_cntl);
962 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET);
964 WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp);
969 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET);
971 WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp);
|
| H A D | sdma_v5_0.c | 666 f32_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));
668 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl);
803 temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));
805 WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), temp);
|
| H A D | sdma_v5_2.c | 472 f32_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));
474 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl);
607 temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL));
609 WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), temp);
|
| H A D | sdma_v4_0.c | 1011 f32_cntl = RREG32_SDMA(i, mmSDMA0_F32_CNTL);
1013 WREG32_SDMA(i, mmSDMA0_F32_CNTL, f32_cntl);
1374 temp = RREG32_SDMA(i, mmSDMA0_F32_CNTL);
1376 WREG32_SDMA(i, mmSDMA0_F32_CNTL, temp);
|
| H A D | sdma_v3_0.c | 620 f32_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]);
625 WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], f32_cntl);
|
| /openbsd-current/sys/dev/pci/drm/amd/include/asic_reg/sdma0/ |
| H A D | sdma0_4_1_offset.h | 96 #define mmSDMA0_F32_CNTL 0x002a macro
|
| H A D | sdma0_4_0_offset.h | 98 #define mmSDMA0_F32_CNTL 0x002a macro
|
| H A D | sdma0_4_2_2_offset.h | 98 #define mmSDMA0_F32_CNTL 0x002a macro
|
| H A D | sdma0_4_2_offset.h | 98 #define mmSDMA0_F32_CNTL 0x002a macro
|
| /openbsd-current/sys/dev/pci/drm/amd/include/asic_reg/oss/ |
| H A D | oss_2_4_d.h | 174 #define mmSDMA0_F32_CNTL 0x3412 macro
|
| H A D | oss_2_0_d.h | 237 #define mmSDMA0_F32_CNTL 0x3412 macro
|
| H A D | oss_3_0_1_d.h | 172 #define mmSDMA0_F32_CNTL 0x3412 macro
|
| H A D | oss_3_0_d.h | 309 #define mmSDMA0_F32_CNTL 0x3412 macro
|
| /openbsd-current/sys/dev/pci/drm/amd/include/asic_reg/gc/ |
| H A D | gc_10_3_0_offset.h | 80 #define mmSDMA0_F32_CNTL 0x002a macro
[all...] |
| H A D | gc_10_1_0_offset.h | 73 #define mmSDMA0_F32_CNTL 0x002a macro
[all...] |
Completed in 509 milliseconds