Searched refs:mmRLC_SRM_INDEX_CNTL_ADDR_0 (Results 1 - 9 of 9) sorted by relevance
| /openbsd-current/sys/dev/pci/drm/amd/amdgpu/ |
| H A D | gfx_v9_0.c | 724 mmRLC_SRM_INDEX_CNTL_ADDR_0 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
725 mmRLC_SRM_INDEX_CNTL_ADDR_1 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
726 mmRLC_SRM_INDEX_CNTL_ADDR_2 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
727 mmRLC_SRM_INDEX_CNTL_ADDR_3 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
728 mmRLC_SRM_INDEX_CNTL_ADDR_4 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
729 mmRLC_SRM_INDEX_CNTL_ADDR_5 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
730 mmRLC_SRM_INDEX_CNTL_ADDR_6 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
731 mmRLC_SRM_INDEX_CNTL_ADDR_7 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
2621 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_INDEX_CNTL_ADDR_0)
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| H A D | gfx_v8_0.c | 3978 temp = mmRLC_SRM_INDEX_CNTL_ADDR_0;
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| /openbsd-current/sys/dev/pci/drm/amd/include/asic_reg/gca/ |
| H A D | gfx_8_0_d.h | 1463 #define mmRLC_SRM_INDEX_CNTL_ADDR_0 0xec8b macro
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| H A D | gfx_8_1_d.h | 1459 #define mmRLC_SRM_INDEX_CNTL_ADDR_0 0xec8b macro
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| /openbsd-current/sys/dev/pci/drm/amd/include/asic_reg/gc/ |
| H A D | gc_9_2_1_offset.h | 6357 #define mmRLC_SRM_INDEX_CNTL_ADDR_0 0x4c8b macro
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| H A D | gc_9_1_offset.h | 6381 #define mmRLC_SRM_INDEX_CNTL_ADDR_0 0x4c8b macro
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| H A D | gc_9_0_offset.h | 6159 #define mmRLC_SRM_INDEX_CNTL_ADDR_0 0x4c8b macro
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| H A D | gc_10_3_0_offset.h | 9317 #define mmRLC_SRM_INDEX_CNTL_ADDR_0 0x4c8b macro
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| H A D | gc_10_1_0_offset.h | 9483 #define mmRLC_SRM_INDEX_CNTL_ADDR_0 0x4c8b macro
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