Searched refs:mmRLC_GPM_SCRATCH_DATA (Results 1 - 12 of 12) sorted by relevance

/openbsd-current/sys/dev/pci/drm/amd/amdgpu/
H A Dgfx_v9_0.c2579 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA),
2585 WREG32_SOC15(GC, 0, mmRLC_GPM_SCRATCH_DATA, register_list_format[i++]);
2589 WREG32_SOC15(GC, 0, mmRLC_GPM_SCRATCH_DATA, register_list_format[i++]);
2590 WREG32_SOC15(GC, 0, mmRLC_GPM_SCRATCH_DATA, register_list_format[i++]);
2594 WREG32_SOC15(GC, 0, mmRLC_GPM_SCRATCH_DATA, j);
2609 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA), list_size);
2615 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA),
H A Dgfx_v7_0.c3833 WREG32(mmRLC_GPM_SCRATCH_DATA, upper_32_bits(adev->gfx.rlc.clear_state_gpu_addr));
3834 WREG32(mmRLC_GPM_SCRATCH_DATA, lower_32_bits(adev->gfx.rlc.clear_state_gpu_addr));
3835 WREG32(mmRLC_GPM_SCRATCH_DATA, adev->gfx.rlc.clear_state_size);
3839 WREG32(mmRLC_GPM_SCRATCH_DATA, 0);
3844 WREG32(mmRLC_GPM_SCRATCH_DATA, adev->gfx.rlc.reg_list[i]);
H A Dgfx_v8_0.c3963 WREG32(mmRLC_GPM_SCRATCH_DATA, register_list_format[i]);
3968 WREG32(mmRLC_GPM_SCRATCH_DATA, list_size);
3974 WREG32(mmRLC_GPM_SCRATCH_DATA,
/openbsd-current/sys/dev/pci/drm/amd/include/asic_reg/gca/
H A Dgfx_7_0_d.h1317 #define mmRLC_GPM_SCRATCH_DATA 0x312d macro
H A Dgfx_7_2_d.h1330 #define mmRLC_GPM_SCRATCH_DATA 0x312d macro
H A Dgfx_8_0_d.h1430 #define mmRLC_GPM_SCRATCH_DATA 0xec6d macro
H A Dgfx_8_1_d.h1427 #define mmRLC_GPM_SCRATCH_DATA 0xec6d macro
/openbsd-current/sys/dev/pci/drm/amd/include/asic_reg/gc/
H A Dgc_9_2_1_offset.h6311 #define mmRLC_GPM_SCRATCH_DATA 0x4c6d macro
H A Dgc_9_1_offset.h6333 #define mmRLC_GPM_SCRATCH_DATA 0x4c6d macro
H A Dgc_9_0_offset.h6111 #define mmRLC_GPM_SCRATCH_DATA 0x4c6d macro
H A Dgc_10_3_0_offset.h10215 #define mmRLC_GPM_SCRATCH_DATA macro
[all...]
H A Dgc_10_1_0_offset.h10483 #define mmRLC_GPM_SCRATCH_DATA macro
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