Searched refs:mmOTG5_OTG_INTERRUPT_CONTROL (Results 1 - 4 of 4) sorted by relevance

/openbsd-current/sys/dev/pci/drm/amd/include/asic_reg/dcn/
H A Ddcn_1_0_offset.h7457 #define mmOTG5_OTG_INTERRUPT_CONTROL 0x1dd9 macro
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H A Ddcn_2_1_0_offset.h9095 #define mmOTG5_OTG_INTERRUPT_CONTROL 0x1dd9 macro
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H A Ddcn_2_0_0_offset.h10126 #define mmOTG5_OTG_INTERRUPT_CONTROL 0x1dd9 macro
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H A Ddcn_3_0_0_offset.h9847 #define mmOTG5_OTG_INTERRUPT_CONTROL 0x1dd9 macro
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