Searched refs:mmMP1_SMN_C2PMSG_54 (Results 1 - 7 of 7) sorted by relevance

/openbsd-current/sys/dev/pci/drm/amd/include/asic_reg/mp/
H A Dmp_10_0_offset.h226 #define mmMP1_SMN_C2PMSG_54 0x0276 macro
H A Dmp_9_0_offset.h238 #define mmMP1_SMN_C2PMSG_54 0x0276 macro
H A Dmp_12_0_0_offset.h226 #define mmMP1_SMN_C2PMSG_54 0x0276 macro
H A Dmp_11_0_8_offset.h226 #define mmMP1_SMN_C2PMSG_54 0x0276 macro
H A Dmp_11_0_offset.h228 #define mmMP1_SMN_C2PMSG_54 0x0276 macro
H A Dmp_11_5_0_offset.h226 #define mmMP1_SMN_C2PMSG_54 0x0276 macro
/openbsd-current/sys/dev/pci/drm/amd/pm/swsmu/smu13/
H A Dsmu_v13_0_0_ppt.c88 #define mmMP1_SMN_C2PMSG_54 0x0276 macro
2493 smu->debug_resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_54);

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