Searched refs:mmMP0_SMN_C2PMSG_33 (Results 1 - 10 of 10) sorted by relevance

/openbsd-current/sys/dev/pci/drm/amd/include/asic_reg/mp/
H A Dmp_10_0_offset.h30 #define mmMP0_SMN_C2PMSG_33 0x0061 macro
H A Dmp_9_0_offset.h30 #define mmMP0_SMN_C2PMSG_33 0x0061 macro
H A Dmp_12_0_0_offset.h30 #define mmMP0_SMN_C2PMSG_33 0x0061 macro
H A Dmp_11_0_8_offset.h30 #define mmMP0_SMN_C2PMSG_33 0x0061 macro
H A Dmp_11_0_offset.h30 #define mmMP0_SMN_C2PMSG_33 0x0061 macro
H A Dmp_11_5_0_offset.h30 #define mmMP0_SMN_C2PMSG_33 0x0061 macro
/openbsd-current/sys/dev/pci/drm/amd/amdgpu/
H A Dpsp_v12_0.c302 offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_33);
H A Dpsp_v3_1.c326 offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_33);
H A Dpsp_v11_0.c395 offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_33);
H A Damdgpu_discovery.c96 #define mmMP0_SMN_C2PMSG_33 0x16061 macro
252 msg = RREG32(mmMP0_SMN_C2PMSG_33);

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