Searched refs:mmMP0_SMN_C2PMSG_101 (Results 1 - 10 of 10) sorted by relevance
| /openbsd-current/sys/dev/pci/drm/amd/amdgpu/ |
| H A D | psp_v11_0_8.c | 39 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
44 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
83 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
90 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
164 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
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| H A D | psp_v12_0.c | 200 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
207 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
244 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
255 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
335 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, GFX_CTRL_CMD_ID_CONSUME_CMD);
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| H A D | psp_v3_1.c | 214 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, psp_ring_reg);
221 mmMP0_SMN_C2PMSG_101), 0x80000000,
259 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
270 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
359 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
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| H A D | psp_v11_0.c | 268 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
279 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
312 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
319 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
583 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, GFX_CTRL_CMD_ID_CONSUME_CMD);
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| /openbsd-current/sys/dev/pci/drm/amd/include/asic_reg/mp/ |
| H A D | mp_10_0_offset.h | 166 #define mmMP0_SMN_C2PMSG_101 0x00a5 macro
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| H A D | mp_9_0_offset.h | 166 #define mmMP0_SMN_C2PMSG_101 0x00a5 macro
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| H A D | mp_12_0_0_offset.h | 166 #define mmMP0_SMN_C2PMSG_101 0x00a5 macro
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| H A D | mp_11_0_8_offset.h | 166 #define mmMP0_SMN_C2PMSG_101 0x00a5 macro
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| H A D | mp_11_0_offset.h | 166 #define mmMP0_SMN_C2PMSG_101 0x00a5 macro
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| H A D | mp_11_5_0_offset.h | 166 #define mmMP0_SMN_C2PMSG_101 0x00a5 macro
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