Searched refs:mmMC_VM_CACHEABLE_DRAM_ADDRESS_START_BASE_IDX (Results 1 - 6 of 6) sorted by relevance

/openbsd-current/sys/dev/pci/drm/amd/include/asic_reg/mmhub/
H A Dmmhub_9_1_offset.h1949 #define mmMC_VM_CACHEABLE_DRAM_ADDRESS_START_BASE_IDX 0 macro
H A Dmmhub_9_3_0_offset.h1937 #define mmMC_VM_CACHEABLE_DRAM_ADDRESS_START_BASE_IDX 0 macro
H A Dmmhub_1_0_offset.h1917 #define mmMC_VM_CACHEABLE_DRAM_ADDRESS_START_BASE_IDX 0 macro
/openbsd-current/sys/dev/pci/drm/amd/include/asic_reg/gc/
H A Dgc_9_2_1_offset.h1626 #define mmMC_VM_CACHEABLE_DRAM_ADDRESS_START_BASE_IDX 0 macro
H A Dgc_9_1_offset.h1688 #define mmMC_VM_CACHEABLE_DRAM_ADDRESS_START_BASE_IDX 0 macro
H A Dgc_9_0_offset.h1669 #define mmMC_VM_CACHEABLE_DRAM_ADDRESS_START_BASE_IDX 0 macro

Completed in 603 milliseconds