Searched refs:mmMAILBOX_INT_CNTL (Results 1 - 7 of 7) sorted by relevance

/openbsd-current/sys/dev/pci/drm/amd/amdgpu/
H A Dmxgpu_nv.h80 #define mmMAILBOX_INT_CNTL 0xE5F macro
H A Dmxgpu_nv.c262 u32 tmp = RREG32_NO_KIQ(mmMAILBOX_INT_CNTL);
269 WREG32_NO_KIQ(mmMAILBOX_INT_CNTL, tmp);
328 u32 tmp = RREG32_NO_KIQ(mmMAILBOX_INT_CNTL);
335 WREG32_NO_KIQ(mmMAILBOX_INT_CNTL, tmp);
H A Dmxgpu_vi.c504 u32 tmp = RREG32_NO_KIQ(mmMAILBOX_INT_CNTL);
508 WREG32_NO_KIQ(mmMAILBOX_INT_CNTL, tmp);
542 u32 tmp = RREG32_NO_KIQ(mmMAILBOX_INT_CNTL);
546 WREG32_NO_KIQ(mmMAILBOX_INT_CNTL, tmp);
/openbsd-current/sys/dev/pci/drm/amd/include/asic_reg/bif/
H A Dbif_5_0_d.h187 #define mmMAILBOX_INT_CNTL 0x14d1 macro
/openbsd-current/sys/dev/pci/drm/amd/include/asic_reg/nbif/
H A Dnbif_6_1_offset.h1151 #define mmMAILBOX_INT_CNTL 0x0e5f // duplicate macro
/openbsd-current/sys/dev/pci/drm/amd/include/asic_reg/nbio/
H A Dnbio_7_4_offset.h2934 #define mmMAILBOX_INT_CNTL 0x013f macro
H A Dnbio_7_0_offset.h4504 #define mmMAILBOX_INT_CNTL 0x013f macro

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