Searched refs:mmIH_RB_WPTR_ADDR_LO (Results 1 - 16 of 16) sorted by relevance

/openbsd-current/sys/dev/pci/drm/amd/include/asic_reg/oss/
H A Doss_1_0_d.h235 #define mmIH_RB_WPTR_ADDR_LO 0x0F85 macro
H A Dosssys_4_0_1_offset.h132 #define mmIH_RB_WPTR_ADDR_LO 0x0086 macro
H A Dosssys_4_0_offset.h132 #define mmIH_RB_WPTR_ADDR_LO 0x0086 macro
H A Dosssys_5_0_0_offset.h132 #define mmIH_RB_WPTR_ADDR_LO 0x0086 macro
H A Dosssys_4_2_0_offset.h134 #define mmIH_RB_WPTR_ADDR_LO 0x0086 macro
H A Doss_2_4_d.h48 #define mmIH_RB_WPTR_ADDR_LO 0xe35 macro
H A Doss_2_0_d.h48 #define mmIH_RB_WPTR_ADDR_LO 0xf85 macro
H A Doss_3_0_1_d.h48 #define mmIH_RB_WPTR_ADDR_LO 0xe35 macro
H A Doss_3_0_d.h48 #define mmIH_RB_WPTR_ADDR_LO 0xe35 macro
/openbsd-current/sys/dev/pci/drm/amd/amdgpu/
H A Dcik_ih.c136 WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(ih->wptr_addr));
H A Dtonga_ih.c138 WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(ih->wptr_addr));
H A Diceland_ih.c138 WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(ih->wptr_addr));
H A Dcz_ih.c138 WREG32(mmIH_RB_WPTR_ADDR_LO, lower_32_bits(ih->wptr_addr));
H A Dvega20_ih.c67 ih_regs->ih_rb_wptr_addr_lo = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO);
H A Dnavi10_ih.c61 ih_regs->ih_rb_wptr_addr_lo = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO);
H A Dvega10_ih.c59 ih_regs->ih_rb_wptr_addr_lo = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO);

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