Searched refs:mmDSCL5_SCL_COEF_RAM_TAP_SELECT (Results 1 - 2 of 2) sorted by relevance

/openbsd-current/sys/dev/pci/drm/amd/include/asic_reg/dcn/
H A Ddcn_2_0_0_offset.h15534 #define mmDSCL5_SCL_COEF_RAM_TAP_SELECT macro
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H A Ddcn_3_0_0_offset.h7387 #define mmDSCL5_SCL_COEF_RAM_TAP_SELECT 0x1410 macro
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