Searched refs:mmD6VGA_CONTROL (Results 1 - 19 of 19) sorted by relevance

/openbsd-current/sys/dev/pci/drm/amd/display/dc/dce120/
H A Ddce120_timing_generator.c410 offset = mmD6VGA_CONTROL - mmD1VGA_CONTROL;
/openbsd-current/sys/dev/pci/drm/amd/display/dc/dce110/
H A Ddce110_timing_generator.c1822 addr = mmD6VGA_CONTROL;
/openbsd-current/sys/dev/pci/drm/amd/amdgpu/
H A Ddce_v11_0.c1863 mmD6VGA_CONTROL,
H A Ddce_v10_0.c1813 mmD6VGA_CONTROL,
H A Ddce_v8_0.c1746 mmD6VGA_CONTROL,
H A Ddce_v6_0.c1786 mmD6VGA_CONTROL,
/openbsd-current/sys/dev/pci/drm/amd/include/asic_reg/dce/
H A Ddce_6_0_d.h1046 #define mmD6VGA_CONTROL 0x00FB macro
H A Ddce_8_0_d.h5149 #define mmD6VGA_CONTROL 0xfb macro
H A Ddce_10_0_d.h6032 #define mmD6VGA_CONTROL 0xfb macro
H A Ddce_11_2_d.h7783 #define mmD6VGA_CONTROL 0xfb macro
H A Ddce_11_0_d.h6109 #define mmD6VGA_CONTROL 0xfb macro
H A Ddce_12_0_offset.h646 #define mmD6VGA_CONTROL 0x003b macro
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/openbsd-current/sys/dev/pci/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_0_3_offset.h109 #define mmD6VGA_CONTROL 0x003b macro
H A Ddcn_1_0_offset.h456 #define mmD6VGA_CONTROL 0x003b macro
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H A Ddcn_2_1_0_offset.h144 #define mmD6VGA_CONTROL 0x003b macro
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H A Ddcn_3_0_1_offset.h192 #define mmD6VGA_CONTROL 0x003b macro
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H A Ddcn_2_0_0_offset.h124 #define mmD6VGA_CONTROL 0x003b macro
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H A Ddcn_3_0_0_offset.h106 #define mmD6VGA_CONTROL 0x003b macro
[all...]
H A Ddcn_3_0_2_offset.h124 #define mmD6VGA_CONTROL 0x003b macro
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