Searched refs:mmCP_RB2_RPTR_ADDR_HI (Results 1 - 11 of 11) sorted by relevance

/openbsd-current/sys/dev/pci/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_d.h510 #define mmCP_RB2_RPTR_ADDR_HI 0x3068 macro
H A Dgfx_7_0_d.h213 #define mmCP_RB2_RPTR_ADDR_HI 0x3068 macro
H A Dgfx_7_2_d.h213 #define mmCP_RB2_RPTR_ADDR_HI 0x3068 macro
H A Dgfx_8_0_d.h237 #define mmCP_RB2_RPTR_ADDR_HI 0x3068 macro
H A Dgfx_8_1_d.h238 #define mmCP_RB2_RPTR_ADDR_HI 0x3068 macro
/openbsd-current/sys/dev/pci/drm/amd/amdgpu/
H A Dgfx_v6_0.c2189 WREG32(mmCP_RB2_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF);
/openbsd-current/sys/dev/pci/drm/amd/include/asic_reg/gc/
H A Dgc_9_2_1_offset.h2677 #define mmCP_RB2_RPTR_ADDR_HI 0x1068 macro
H A Dgc_9_1_offset.h2739 #define mmCP_RB2_RPTR_ADDR_HI 0x1068 macro
H A Dgc_9_0_offset.h2462 #define mmCP_RB2_RPTR_ADDR_HI 0x1068 macro
H A Dgc_10_3_0_offset.h4458 #define mmCP_RB2_RPTR_ADDR_HI 0x1e08 macro
[all...]
H A Dgc_10_1_0_offset.h4805 #define mmCP_RB2_RPTR_ADDR_HI 0x1e08 macro
[all...]

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