Searched refs:mmCP_MEC_ME1_UCODE_ADDR (Results 1 - 12 of 12) sorted by relevance

/openbsd-current/sys/dev/pci/drm/amd/include/asic_reg/gca/
H A Dgfx_7_0_d.h250 #define mmCP_MEC_ME1_UCODE_ADDR 0x305c macro
H A Dgfx_7_2_d.h252 #define mmCP_MEC_ME1_UCODE_ADDR 0x305c macro
H A Dgfx_8_0_d.h281 #define mmCP_MEC_ME1_UCODE_ADDR 0xf81a macro
H A Dgfx_8_1_d.h282 #define mmCP_MEC_ME1_UCODE_ADDR 0xf81a macro
/openbsd-current/sys/dev/pci/drm/amd/amdgpu/
H A Dgfx_v7_0.c2669 WREG32(mmCP_MEC_ME1_UCODE_ADDR, 0);
2672 WREG32(mmCP_MEC_ME1_UCODE_ADDR, 0);
H A Dgfx_v9_0.c3203 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR,
3209 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR,
H A Dgfx_v10_0.c6282 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, 0);
6288 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version);
/openbsd-current/sys/dev/pci/drm/amd/include/asic_reg/gc/
H A Dgc_9_2_1_offset.h6995 #define mmCP_MEC_ME1_UCODE_ADDR 0x581a macro
H A Dgc_9_1_offset.h6967 #define mmCP_MEC_ME1_UCODE_ADDR 0x581a macro
H A Dgc_9_0_offset.h6743 #define mmCP_MEC_ME1_UCODE_ADDR 0x581a macro
H A Dgc_10_3_0_offset.h9961 #define mmCP_MEC_ME1_UCODE_ADDR 0x581a macro
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H A Dgc_10_1_0_offset.h10245 #define mmCP_MEC_ME1_UCODE_ADDR macro
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