Searched refs:mmCC_GC_SHADER_ARRAY_CONFIG (Results 1 - 15 of 15) sorted by relevance

/openbsd-current/sys/dev/pci/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_d.h291 #define mmCC_GC_SHADER_ARRAY_CONFIG 0x226F macro
H A Dgfx_7_0_d.h2337 #define mmCC_GC_SHADER_ARRAY_CONFIG 0x226f macro
H A Dgfx_7_2_d.h2361 #define mmCC_GC_SHADER_ARRAY_CONFIG 0x226f macro
H A Dgfx_8_0_d.h2601 #define mmCC_GC_SHADER_ARRAY_CONFIG 0x226f macro
H A Dgfx_8_1_d.h2580 #define mmCC_GC_SHADER_ARRAY_CONFIG 0x226f macro
/openbsd-current/sys/dev/pci/drm/amd/amdgpu/
H A Dgfx_v6_0.c1521 data = RREG32(mmCC_GC_SHADER_ARRAY_CONFIG) |
H A Dgfx_v7_0.c3772 data = RREG32(mmCC_GC_SHADER_ARRAY_CONFIG);
H A Dgfx_v8_0.c7088 data = RREG32(mmCC_GC_SHADER_ARRAY_CONFIG) |
H A Dgfx_v9_0.c7187 data = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG);
H A Dgfx_v10_0.c9385 efuse_setting = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG);
/openbsd-current/sys/dev/pci/drm/amd/include/asic_reg/gc/
H A Dgc_9_2_1_offset.h309 #define mmCC_GC_SHADER_ARRAY_CONFIG 0x026f macro
H A Dgc_9_1_offset.h315 #define mmCC_GC_SHADER_ARRAY_CONFIG 0x026f macro
H A Dgc_9_0_offset.h319 #define mmCC_GC_SHADER_ARRAY_CONFIG 0x026f macro
H A Dgc_10_3_0_offset.h2430 #define mmCC_GC_SHADER_ARRAY_CONFIG 0x100f macro
[all...]
H A Dgc_10_1_0_offset.h2341 #define mmCC_GC_SHADER_ARRAY_CONFIG 0x100f macro
[all...]

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