Searched refs:mmBIF_SDMA0_DOORBELL_RANGE (Results 1 - 9 of 9) sorted by relevance

/openbsd-current/sys/dev/pci/drm/amd/amdgpu/
H A Dnbio_v7_4.c146 SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE);
162 mmBIF_SDMA0_DOORBELL_RANGE);
166 mmBIF_SDMA0_DOORBELL_RANGE);
H A Dnbio_v7_0.c71 u32 reg = instance == 0 ? SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE) :
H A Dnbio_v6_1.c92 u32 reg = instance == 0 ? SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE) :
H A Dnbio_v2_3.c113 u32 reg = instance == 0 ? SOC15_REG_OFFSET(NBIO, 0, mmBIF_SDMA0_DOORBELL_RANGE) :
/openbsd-current/sys/dev/pci/drm/amd/include/asic_reg/nbif/
H A Dnbif_6_1_offset.h363 #define mmBIF_SDMA0_DOORBELL_RANGE 0x4f0af0 // duplicate macro
/openbsd-current/sys/dev/pci/drm/amd/include/asic_reg/nbio/
H A Dnbio_6_1_offset.h2638 #define mmBIF_SDMA0_DOORBELL_RANGE 0x01d0 macro
H A Dnbio_7_4_offset.h2954 #define mmBIF_SDMA0_DOORBELL_RANGE 0x01d0 macro
H A Dnbio_7_0_offset.h4522 #define mmBIF_SDMA0_DOORBELL_RANGE 0x01d0 macro
H A Dnbio_2_3_offset.h648 #define mmBIF_SDMA0_DOORBELL_RANGE 0x01d0 macro
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