Searched refs:mmBIF_BX_PF0_MAILBOX_INT_CNTL (Results 1 - 2 of 2) sorted by relevance
| /netbsd-current/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| H A D | amdgpu_mxgpu_ai.c | 232 u32 tmp = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_INT_CNTL));
236 WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_INT_CNTL), tmp);
285 u32 tmp = RREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_INT_CNTL));
289 WREG32_NO_KIQ(SOC15_REG_OFFSET(NBIO, 0, mmBIF_BX_PF0_MAILBOX_INT_CNTL), tmp);
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| /netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/nbio/ |
| H A D | nbio_6_1_offset.h | 2622 #define mmBIF_BX_PF0_MAILBOX_INT_CNTL 0x013f macro
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