Searched refs:mmATC_L2_CACHE_2M_DSM_CNTL (Results 1 - 2 of 2) sorted by relevance
| /netbsd-current/sys/external/bsd/drm2/dist/drm/amd/include/asic_reg/gc/ |
| H A D | gc_9_4_1_offset.h | 240 #define mmATC_L2_CACHE_2M_DSM_CNTL 0x0811 macro
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| /netbsd-current/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| H A D | amdgpu_gfx_v9_4.c | 708 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_DSM_CNTL, 0);
710 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_DSM_CNTL, 0);
773 data = RREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_DSM_CNTL);
927 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_DSM_CNTL, 0);
929 WREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_DSM_CNTL, 0);
948 RREG32_SOC15(GC, 0, mmATC_L2_CACHE_2M_DSM_CNTL);
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