/openbsd-current/sys/dev/pci/drm/i915/display/ |
H A D | intel_wm.c | 24 * lines), so need to account for TLB latency 27 * watermark = dotclock * bytes per pixel * latency 28 * where latency is platform & configuration dependent (we assume pessimal 32 * watermark = (trunc(latency/line time)+1) * surface width * 37 * and latency is assumed to be high, as above. 152 unsigned int latency = wm[level]; local 154 if (latency == 0) { 156 "%s WM%d latency not provided\n", 163 * - before then, WM1+ latency values are in 0.5us units 166 latency * 192 unsigned int latency = wm[level]; local [all...] |
H A D | skl_watermark.c | 123 /* avoid overflow when adding with wm0 latency/etc. */ 707 unsigned int latency, 715 unsigned int latency = i915->display.wm.skl_latency[level]; local 717 if (latency == 0) 726 latency += 4; 729 latency += 15; 731 return latency; 753 unsigned int latency = skl_wm_latency(i915, level, &wp); local 755 skl_compute_plane_wm(crtc_state, plane, level, latency, &wp, &wm, &wm); 1658 * The max latency shoul 1664 skl_wm_method1(const struct drm_i915_private *i915, u32 pixel_rate, u8 cpp, u32 latency, u32 dbuf_block_size) argument 1683 skl_wm_method2(u32 pixel_rate, u32 pipe_htotal, u32 latency, uint_fixed_16_16_t plane_blocks_per_line) argument 1849 skl_compute_plane_wm(const struct intel_crtc_state *crtc_state, struct intel_plane *plane, int level, unsigned int latency, const struct skl_wm_params *wp, const struct skl_wm_level *result_prev, struct skl_wm_level *result ) argument 1995 unsigned int latency = skl_wm_latency(i915, level, wm_params); local 2012 unsigned int latency = 0; local 2209 skl_is_vblank_too_short(const struct intel_crtc_state *crtc_state, int wm0_lines, int latency) argument 2246 int latency; local [all...] |
H A D | i9xx_wm.c | 78 const struct cxsr_latency *latency; local 85 latency = &cxsr_latency_table[i]; 86 if (is_desktop == latency->is_desktop && 87 is_ddr3 == latency->is_ddr3 && 88 fsb == latency->fsb_freq && mem == latency->mem_freq) 89 return latency; 255 * platforms but not overly aggressive on lower latency configs. 434 * @latency: Memory wakeup latency i 463 intel_wm_method1(unsigned int pixel_rate, unsigned int cpp, unsigned int latency) argument 505 intel_wm_method2(unsigned int pixel_rate, unsigned int htotal, unsigned int width, unsigned int cpp, unsigned int latency) argument 633 const struct cxsr_latency *latency; local 881 unsigned int latency = dev_priv->display.wm.pri_latency[level] * 10; local 1370 vlv_wm_method2(unsigned int pixel_rate, unsigned int htotal, unsigned int width, unsigned int cpp, unsigned int latency) argument 2262 ilk_wm_method1(unsigned int pixel_rate, unsigned int cpp, unsigned int latency) argument 2275 ilk_wm_method2(unsigned int pixel_rate, unsigned int htotal, unsigned int width, unsigned int cpp, unsigned int latency) argument [all...] |
/openbsd-current/sys/dev/pci/bktr/ |
H A D | bktr_os.c | 156 u_int latency; local 219 * PCI latency timer. 32 is a good value for 4 bus mastering slots, if 225 latency = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_LATENCY_TIMER); 226 latency = (latency >> 8) & 0xff; 228 if (!latency) { 230 printf("%s: PCI bus latency was 0 changing to %d", 233 latency = BROOKTREE_DEF_LATENCY_VALUE; 235 PCI_LATENCY_TIMER, latency<<8);
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/openbsd-current/gnu/gcc/gcc/ |
H A D | ddg.h | 96 int latency; member in struct:ddg_edge
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H A D | ddg.c | 148 /* Computes the dependence parameters (latency, distance etc.), creates 155 int latency, distance = 0; 174 latency = insn_cost (src_node->insn, link, dest_node->insn); 176 e = create_ddg_edge (src_node, dest_node, t, dt, latency, distance); 566 dep_c, e->latency, e->distance, INSN_UID (e->dest->insn)); 620 fprintf (file, "label: \"%d_%d\"}\n", e->latency, e->distance); 637 e->latency = l; 688 length += backarc->latency; 991 at-least as large as the count of U_NODE plus the latency between them. 1007 && (v_node->aux.count < u_node->aux.count + e->latency)) 154 int latency, distance = 0; local [all...] |
H A D | expmed.c | 2353 The "latency" field holds the minimum possible latency of the 2357 any leaf to the root. Hence latency(a op b) is defined as zero for 2358 leaves and rtx_cost(op) + max(latency(a), latency(b)) otherwise. */ 2362 short latency; /* The latency of the multiplication sequence. */ 2369 || ((X)->cost == (Y) && (X)->latency < (Y))) 2374 lower "cost". If "cost"s are tied, the lower latency is cheaper. */ 2377 && (X)->latency < ( 2352 short latency; /* The latency of the multiplication sequence. */ member in struct:mult_cost [all...] |
H A D | modulo-sched.c | 403 longest latency edge for each node. Reset based on experiments. */ 417 max_edge_latency = MAX (max_edge_latency, e->latency); 1287 'l(u)' is the latency of u. 1393 + e->latency - (e->distance * ii); 1417 SCHED_TIME (v_node) - e->latency 1442 SCHED_TIME (v_node) + e->latency 1455 SCHED_TIME (v_node) - e->latency 1573 && e->latency == (ii * e->distance) 1579 && e->latency == (ii * e->distance) 1797 ASAP (e->src) + e->latency); [all...] |
H A D | genautomata.c | 383 int latency; 1322 DECL_BYPASS (decl)->latency = XINT (def, 0); 2423 automata) and correctness of their attributes (insn latency times 2431 error ("define_insn_reservation `%s' has negative latency time", 2442 if (DECL_BYPASS (decl)->latency < 0) 2443 error ("define_bypass `%s - %s' has negative latency time", 2526 if (DECL_BYPASS (decl)->latency == bypass->latency) 7696 int i, max, latency; 7705 latency 379 int latency; member in struct:bypass_decl 7668 int i, max, latency; local [all...] |
/openbsd-current/sys/dev/pci/drm/amd/include/ |
H A D | dm_pp_interface.h | 105 * Memory clock DPMS with this latency or below is allowed, DPMS with 106 * higher latency not allowed. 166 uint32_t latency[MAX_NUM_CLOCKS]; member in struct:amd_pp_clocks
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/openbsd-current/gnu/gcc/gcc/config/ia64/ |
H A D | lib1funcs.asm | 31 // From the Intel IA-64 Optimization Guide, choose the minimum latency 77 // From the Intel IA-64 Optimization Guide, choose the minimum latency 119 // From the Intel IA-64 Optimization Guide, choose the minimum latency 155 // From the Intel IA-64 Optimization Guide, choose the minimum latency 208 // From the Intel IA-64 Optimization Guide, choose the minimum latency 265 // From the Intel IA-64 Optimization Guide, choose the minimum latency 318 // From the Intel IA-64 Optimization Guide, choose the minimum latency 376 // From the Intel IA-64 Optimization Guide, choose the minimum latency 422 // From the Intel IA-64 Optimization Guide, choose the minimum latency 472 // From the Intel IA-64 Optimization Guide, choose the minimum latency [all...] |
/openbsd-current/gnu/usr.bin/gcc/gcc/config/ia64/ |
H A D | lib1funcs.asm | 4 // From the Intel IA-64 Optimization Guide, choose the minimum latency 46 // From the Intel IA-64 Optimization Guide, choose the minimum latency 88 // From the Intel IA-64 Optimization Guide, choose the minimum latency 124 // From the Intel IA-64 Optimization Guide, choose the minimum latency 174 // From the Intel IA-64 Optimization Guide, choose the minimum latency 228 // From the Intel IA-64 Optimization Guide, choose the minimum latency 278 // From the Intel IA-64 Optimization Guide, choose the minimum latency 333 // From the Intel IA-64 Optimization Guide, choose the minimum latency 376 // From the Intel IA-64 Optimization Guide, choose the minimum latency 423 // From the Intel IA-64 Optimization Guide, choose the minimum latency [all...] |
/openbsd-current/sys/dev/acpi/ |
H A D | acpicpu.c | 111 u_short latency; member in struct:acpi_cstate 346 int flags, int latency, int power, uint64_t address) 350 dnprintf(10," C%d: latency:.%4x power:%.4x addr:%.16llx\n", 351 state, latency, power, address); 364 cx->latency = latency; 620 printf("@%d%s", cx->latency, meth); 1174 * Find the first state with a latency we'll accept, ignoring 1179 cx->latency * 3 > sc->sc_prev_sleep) { 345 acpicpu_add_cstate(struct acpicpu_softc *sc, int state, int method, int flags, int latency, int power, uint64_t address) argument
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/openbsd-current/sys/dev/pci/drm/amd/pm/powerplay/hwmgr/ |
H A D | smu7_hwmgr.h | 205 uint32_t latency; member in struct:smu7_mclk_latency_entries
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H A D | smu10_hwmgr.h | 179 uint32_t latency; member in struct:smu10_mclk_latency_entries
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H A D | vega10_hwmgr.h | 216 uint32_t latency; member in struct:vega10_mclk_latency_entries
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H A D | vega12_hwmgr.h | 206 uint32_t latency; member in struct:vega12_mclk_latency_entries
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H A D | vega20_hwmgr.h | 267 uint32_t latency; member in struct:vega20_mclk_latency_entries
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H A D | vega12_hwmgr.c | 1896 data->mclk_latency_table.entries[i].latency = 2354 uint32_t i, latency; local 2359 latency = hwmgr->display_config->dce_tolerable_mclk_in_active_latency; 2417 if (data->mclk_latency_table.entries[i].latency <= latency) {
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H A D | vega20_hwmgr.c | 2850 data->mclk_latency_table.entries[i].latency = 3735 uint32_t i, latency; local 3740 latency = hwmgr->display_config->dce_tolerable_mclk_in_active_latency; 3798 if (data->mclk_latency_table.entries[i].latency <= latency) {
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/openbsd-current/sys/dev/pci/drm/amd/display/dc/dce120/ |
H A D | dce120_resource.c | 921 unsigned int latency; local 966 latency = 45; 970 mem_clks.data[i].latency_in_us = latency; 972 latency -= 5;
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/openbsd-current/sys/dev/pci/drm/i915/gt/ |
H A D | intel_engine_pm.c | 103 ewma__engine_latency_add(&rq->engine->latency,
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H A D | intel_engine_types.h | 147 /* A simple estimator for the round-trip latency of an engine */ 455 struct ewma__engine_latency latency; member in struct:intel_engine_cs
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/openbsd-current/gnu/usr.bin/gcc/gcc/ |
H A D | genautomata.c | 760 int latency; 1695 DECL_BYPASS (decl)->latency = XINT (def, 0); 2709 automata) and correctness of their attributes (insn latency times 2719 error ("define_insn_reservation `%s' has negative latency time", 2730 if (DECL_BYPASS (decl)->latency < 0) 2731 error ("define_bypass `%s - %s' has negative latency time", 2814 if (DECL_BYPASS (decl)->latency == bypass->latency) 7988 int i, max, latency; 7997 latency 757 int latency; member in struct:bypass_decl 7961 int i, max, latency; local [all...] |
/openbsd-current/gnu/gcc/gcc/config/sh/ |
H A D | lib1funcs-Os-4-200.asm | 160 (*): r2 is restored in the rts delay slot and has a lingering latency
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