Searched refs:ixDIDT_TD_CTRL2 (Results 1 - 12 of 12) sorted by relevance

/openbsd-current/sys/dev/pci/drm/amd/pm/powerplay/hwmgr/
H A Dsmu7_powertune.c167 { ixDIDT_TD_CTRL2, DIDT_TD_CTRL2__MAX_POWER_DELTA_MASK, DIDT_TD_CTRL2__MAX_POWER_DELTA__SHIFT, 0x3fff, GPU_CONFIGREG_DIDT_IND },
168 { ixDIDT_TD_CTRL2, DIDT_TD_CTRL2__UNUSED_0_MASK, DIDT_TD_CTRL2__UNUSED_0__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
169 { ixDIDT_TD_CTRL2, DIDT_TD_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK, DIDT_TD_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT, 0x000f, GPU_CONFIGREG_DIDT_IND },
170 { ixDIDT_TD_CTRL2, DIDT_TD_CTRL2__UNUSED_1_MASK, DIDT_TD_CTRL2__UNUSED_1__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
171 { ixDIDT_TD_CTRL2, DIDT_TD_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK, DIDT_TD_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
172 { ixDIDT_TD_CTRL2, DIDT_TD_CTRL2__UNUSED_2_MASK, DIDT_TD_CTRL2__UNUSED_2__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
309 { ixDIDT_TD_CTRL2, DIDT_TD_CTRL2__MAX_POWER_DELTA_MASK, DIDT_TD_CTRL2__MAX_POWER_DELTA__SHIFT, 0x3fff, GPU_CONFIGREG_DIDT_IND },
310 { ixDIDT_TD_CTRL2, DIDT_TD_CTRL2__UNUSED_0_MASK, DIDT_TD_CTRL2__UNUSED_0__SHIFT, 0x0000, GPU_CONFIGREG_DIDT_IND },
311 { ixDIDT_TD_CTRL2, DIDT_TD_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK, DIDT_TD_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT, 0x000f, GPU_CONFIGREG_DIDT_IND },
312 { ixDIDT_TD_CTRL2, DIDT_TD_CTRL2__UNUSED_1_MAS
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H A Dvega10_powertune.c132 { ixDIDT_TD_CTRL2, DIDT_TD_CTRL2__MAX_POWER_DELTA_MASK, DIDT_TD_CTRL2__MAX_POWER_DELTA__SHIFT, 0x3fff },
133 { ixDIDT_TD_CTRL2, DIDT_TD_CTRL2__SHORT_TERM_INTERVAL_SIZE_MASK, DIDT_TD_CTRL2__SHORT_TERM_INTERVAL_SIZE__SHIFT, 0x00c0 },
134 { ixDIDT_TD_CTRL2, DIDT_TD_CTRL2__LONG_TERM_INTERVAL_RATIO_MASK, DIDT_TD_CTRL2__LONG_TERM_INTERVAL_RATIO__SHIFT, 0x0001 },
/openbsd-current/sys/dev/pci/drm/amd/include/asic_reg/gca/
H A Dgfx_7_0_d.h2521 #define ixDIDT_TD_CTRL2 0x42 macro
H A Dgfx_7_2_d.h2546 #define ixDIDT_TD_CTRL2 0x42 macro
H A Dgfx_8_0_d.h2793 #define ixDIDT_TD_CTRL2 0x42 macro
H A Dgfx_8_1_d.h2771 #define ixDIDT_TD_CTRL2 0x42 macro
/openbsd-current/sys/dev/pci/drm/amd/include/asic_reg/gc/
H A Dgc_9_2_1_offset.h7439 #define ixDIDT_TD_CTRL2 0x0042 macro
H A Dgc_9_1_offset.h7402 #define ixDIDT_TD_CTRL2 0x0042 macro
H A Dgc_9_0_offset.h7195 #define ixDIDT_TD_CTRL2 0x0042 macro
H A Dgc_9_4_2_offset.h88 #define ixDIDT_TD_CTRL2 0x0042 macro
H A Dgc_10_3_0_offset.h13537 #define ixDIDT_TD_CTRL2 macro
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H A Dgc_10_1_0_offset.h11291 #define ixDIDT_TD_CTRL2 macro
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