| /openbsd-current/gnu/llvm/llvm/utils/TableGen/GlobalISel/ |
| H A D | GIMatchDag.cpp | 62 if (E->getFromMO()->isDef() && !E->getToMO()->isDef())
66 if (E->getFromMO()->isDef() && !E->getToMO()->isDef())
70 if (E->getFromMO()->isDef() == E->getToMO()->isDef())
73 if (E->getFromMO()->isDef() == E->getToMO()->isDef())
75 else if (E->getFromMO()->isDef() && !E->getToMO()->isDef())
[all...] |
| H A D | GIMatchDagEdge.cpp | 24 return FromMO->isDef();
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| H A D | GIMatchDagOperands.cpp | 35 I.value().isDef());
46 if (I.isDef())
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| H A D | GIMatchDagOperands.h | 56 bool isDef() const { return IsDef; } function in class:llvm::GIMatchDagOperand
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| /openbsd-current/gnu/llvm/llvm/lib/CodeGen/ |
| H A D | LiveIntervalCalc.cpp | 56 if (!MO.isDef() && !MO.readsReg())
73 if (MO.isDef())
81 if (MO.isDef() && !LI.hasSubRanges())
156 if (!MO.readsReg() || (IsSubRange && MO.isDef()))
162 if (MO.isDef())
174 assert(!MO.isDef() && "Cannot handle PHI def of partial register.");
182 if (MO.isDef())
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| H A D | LiveRegUnits.cpp | 48 if (MOP.isDef() && MOP.getReg().isPhysical())
75 if (MOP.isDef() || MOP.readsReg())
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| H A D | DeadMachineInstructionElim.cpp | 79 if (MO.isReg() && MO.isDef()) {
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| H A D | MachineInstrBundle.cpp | 156 if (MO.isDef()) {
299 if (MO.isDef())
304 if (MO.isDef())
345 } else if (MO.isDef()) {
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| H A D | MIRCanonicalizerPass.cpp | 161 if (!MO.isDef())
177 if (!MO.isDef())
344 if (!MO.isDef() && MO.isKill()) {
349 if (MO.isDef() && MO.isDead()) {
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| H A D | MachineSSAContext.cpp | 46 if (op.isReg() && op.isDef())
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| H A D | MachineUniformityAnalysis.cpp | 24 if (!op.isReg() || !op.isDef())
39 if (!op.isReg() || !op.isDef())
92 if (op.isReg() && op.isDef() && op.getReg().isVirtual())
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| H A D | RenameIndependentSubregs.cpp | 180 if (!MO.isDef() && !MO.readsReg())
190 Pos = MO.isDef() ? Pos.getRegSlot(MO.isEarlyClobber())
219 if (!MO.isDef() && !MO.readsReg())
224 Pos = MO.isDef() ? Pos.getRegSlot(MO.isEarlyClobber())
346 if (!MO.isDef())
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| H A D | LiveRangeEdit.cpp | 216 if (MO.isDef()) {
317 if (VRM && MI->getOperand(0).isReg() && MI->getOperand(0).isDef() &&
343 else if (MO.isDef())
353 if ((MI->readsVirtualRegister(Reg) && (MI->isCopy() || MO.isDef())) ||
360 if (MO.isDef()) {
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| H A D | MachineOperand.cpp | 95 if (isDef())
130 if (isDef())
255 void MachineOperand::ChangeToRegister(Register Reg, bool isDef, bool isImp, argument
269 if (!isDef && MI && MI->isDebugInstr())
273 assert(!(isDead && !isDef) && "Dead flag on non-def");
274 assert(!(isKill && isDef) && "Kill flag on def");
278 IsDef = isDef;
308 return getReg() == Other.getReg() && isDef() == Other.isDef() &&
375 return hash_combine(MO.getType(), (unsigned)MO.getReg(), MO.getSubReg(), MO.isDef());
[all...] |
| H A D | LivePhysRegs.cpp | 52 if (MOP.isDef())
90 if (O->isDef()) {
295 if (!MO->isReg() || !MO->isDef() || MO->isDebug())
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| /openbsd-current/gnu/llvm/llvm/tools/llvm-reduce/deltas/ |
| H A D | ReduceRegisterDefs.cpp | 51 if (!MO.isReg() || !MO.isDef())
70 if (!MO.isReg() || !MO.isDef())
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| H A D | ReduceInstructionsMIR.cpp | 37 if (!MO.isReg() || !MO.isDef() || MO.isDead())
93 if (!MO.isReg() || !MO.isDef() || MO.isDead())
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| /openbsd-current/gnu/llvm/llvm/tools/llvm-exegesis/lib/ |
| H A D | MCInstrDescView.cpp | 44 bool Operand::isDef() const { return IsDef; } function in class:llvm::exegesis::Operand
173 if (Op.isDef())
177 if (Op.isDef() && Op.isImplicit())
260 if (Op.isDef())
328 if (Op.isReg() && Op.isDef() == SelectDef) {
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| H A D | ParallelSnippetGenerator.cpp | 181 if (Op.isDef()) {
240 if (Op.isDef())
266 assert(Op.isDef() && "Not a use and not a def?");
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| /openbsd-current/gnu/llvm/llvm/include/llvm/CodeGen/ |
| H A D | MachineOperand.h | 293 /// isDef. Sometimes, if the operand is printed before '=', we don't print
381 bool isDef() const { function
799 void ChangeToRegister(Register Reg, bool isDef, bool isImp = false,
830 static MachineOperand CreateReg(Register Reg, bool isDef, bool isImp = false,
837 assert(!(isDead && !isDef) && "Dead flag on non-def");
838 assert(!(isKill && isDef) && "Kill flag on def");
840 Op.IsDef = isDef;
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| H A D | LiveRegUnits.h | 59 if (O->isDef()) {
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| /openbsd-current/gnu/llvm/llvm/lib/Target/AMDGPU/ |
| H A D | SIFormMemoryClauses.cpp | 123 if (!MO.isReg() || MO.isDef())
170 const RegUse &Map = MO.isDef() ? Uses : Defs;
230 RegUse &Map = MO.isDef() ? Defs : Uses;
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| /openbsd-current/gnu/llvm/llvm/lib/Target/X86/ |
| H A D | X86FixupBWInsts.cpp | 266 assert((MO.isDef() || MO.isUse()) && "Expected Def or Use only!");
268 if (MO.isDef() && TRI->isSuperRegisterEq(OrigDestReg, MO.getReg()))
350 if (Op.getReg() != (Op.isDef() ? NewDestReg : NewSrcReg))
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| /openbsd-current/gnu/llvm/llvm/lib/Target/PowerPC/ |
| H A D | PPCCTRLoopsVerify.cpp | 86 if (MO.isDef() && (MO.getReg() == PPC::CTR || MO.getReg() == PPC::CTR8))
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| /openbsd-current/gnu/llvm/llvm/lib/Target/Lanai/ |
| H A D | LanaiDelaySlotFiller.cpp | 208 if (MO.isDef()) {
237 if (MO.isDef())
|