Searched refs:gpu_addr (Results 1 - 25 of 146) sorted by relevance

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/openbsd-current/sys/dev/pci/drm/radeon/
H A Duvd_v4_2.c47 addr = (rdev->uvd.gpu_addr + 0x200) >> 3;
49 addr = rdev->uvd.gpu_addr >> 3;
67 addr = (rdev->uvd.gpu_addr >> 28) & 0xF;
71 addr = (rdev->uvd.gpu_addr >> 32) & 0xFF;
H A Dr600_dma.c143 upper_32_bits(rdev->wb.gpu_addr + R600_WB_DMA_RPTR_OFFSET) & 0xFF);
145 ((rdev->wb.gpu_addr + R600_WB_DMA_RPTR_OFFSET) & 0xFFFFFFFC));
150 WREG32(DMA_RB_BASE, ring->gpu_addr >> 8);
236 u64 gpu_addr; local
243 gpu_addr = rdev->wb.gpu_addr + index;
254 radeon_ring_write(ring, lower_32_bits(gpu_addr));
255 radeon_ring_write(ring, upper_32_bits(gpu_addr) & 0xff);
290 u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
317 u64 addr = semaphore->gpu_addr;
343 u64 gpu_addr; local
[all...]
H A Duvd_v3_1.c44 uint64_t addr = semaphore->gpu_addr;
H A Dradeon_semaphore.c51 (*semaphore)->gpu_addr = radeon_sa_bo_gpu_addr((*semaphore)->sa_bo);
69 ring->last_semaphore_signal_addr = semaphore->gpu_addr;
86 ring->last_semaphore_wait_addr = semaphore->gpu_addr;
H A Duvd_v2_2.c43 uint64_t addr = rdev->fence_drv[fence->ring].gpu_addr;
77 uint64_t addr = semaphore->gpu_addr;
113 addr = rdev->uvd.gpu_addr >> 3;
130 addr = (rdev->uvd.gpu_addr >> 28) & 0xF;
134 addr = (rdev->uvd.gpu_addr >> 32) & 0xFF;
H A Duvd_v1_0.c85 uint64_t addr = rdev->fence_drv[fence->ring].gpu_addr;
121 addr = (rdev->uvd.gpu_addr >> 3) + 16;
138 addr = (rdev->uvd.gpu_addr >> 28) & 0xF;
142 addr = (rdev->uvd.gpu_addr >> 32) & 0xFF;
364 WREG32(UVD_LMI_EXT40_ADDR, upper_32_bits(ring->gpu_addr) |
374 WREG32(UVD_RBC_RB_BASE, ring->gpu_addr);
487 radeon_ring_write(ring, ib->gpu_addr);
H A Devergreen_dma.c44 u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
88 radeon_ring_write(ring, (ib->gpu_addr & 0xFFFFFFE0));
89 radeon_ring_write(ring, (ib->length_dw << 12) | (upper_32_bits(ib->gpu_addr) & 0xFF));
H A Dradeon_object.h146 extern int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr);
148 u64 max_offset, u64 *gpu_addr);
180 return to_radeon_sa_manager(sa_bo->manager)->gpu_addr +
H A Dcik_sdma.c154 radeon_ring_write(ring, ib->gpu_addr & 0xffffffe0); /* base must be 32 byte aligned */
155 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr));
203 u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
232 u64 addr = semaphore->gpu_addr;
400 upper_32_bits(rdev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
402 ((rdev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC));
407 WREG32(SDMA0_GFX_RB_BASE + reg_offset, ring->gpu_addr >> 8);
408 WREG32(SDMA0_GFX_RB_BASE_HI + reg_offset, ring->gpu_addr >> 40);
651 u64 gpu_addr; local
658 gpu_addr
708 u64 gpu_addr; local
[all...]
H A Dradeon_sa.c91 r = radeon_bo_pin(sa_manager->bo, sa_manager->domain, &sa_manager->gpu_addr);
158 drm_suballoc_dump_debug_info(&sa_manager->base, &p, sa_manager->gpu_addr);
H A Dradeon_trace.h177 __field(uint64_t, gpu_addr)
183 __entry->gpu_addr = sem->gpu_addr;
187 __entry->waiters, __entry->gpu_addr)
H A Dvce_v1_0.c218 uint64_t addr = rdev->vce.gpu_addr;
300 WREG32(VCE_RB_BASE_LO, ring->gpu_addr);
301 WREG32(VCE_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
307 WREG32(VCE_RB_BASE_LO2, ring->gpu_addr);
308 WREG32(VCE_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
H A Dni_dma.c144 radeon_ring_write(ring, (ib->gpu_addr & 0xFFFFFFE0));
145 radeon_ring_write(ring, (ib->length_dw << 12) | (upper_32_bits(ib->gpu_addr) & 0xFF));
222 upper_32_bits(rdev->wb.gpu_addr + wb_offset) & 0xFF);
224 ((rdev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC));
229 WREG32(DMA_RB_BASE + reg_offset, ring->gpu_addr >> 8);
/openbsd-current/sys/dev/pci/drm/amd/amdgpu/
H A Damdgpu_sa.c54 &sa_manager->bo, &sa_manager->gpu_addr,
76 amdgpu_bo_free_kernel(&sa_manager->bo, &sa_manager->gpu_addr, &sa_manager->cpu_ptr);
114 drm_suballoc_dump_debug_info(&sa_manager->base, &p, sa_manager->gpu_addr);
H A Damdgpu_ih.c85 ih->gpu_addr = dma_addr;
105 &ih->ring_obj, &ih->gpu_addr,
113 ih->wptr_addr = adev->wb.gpu_addr + wptr_offs * 4;
115 ih->rptr_addr = adev->wb.gpu_addr + rptr_offs * 4;
145 (void *)ih->ring, ih->gpu_addr);
151 amdgpu_bo_free_kernel(&ih->ring_obj, &ih->gpu_addr,
153 amdgpu_device_wb_free(adev, (ih->wptr_addr - ih->gpu_addr) / 4);
154 amdgpu_device_wb_free(adev, (ih->rptr_addr - ih->gpu_addr) / 4);
H A Dvcn_v2_0.c349 lower_32_bits(adev->vcn.inst->gpu_addr));
351 upper_32_bits(adev->vcn.inst->gpu_addr));
361 lower_32_bits(adev->vcn.inst->gpu_addr + offset));
363 upper_32_bits(adev->vcn.inst->gpu_addr + offset));
369 lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
371 upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
377 lower_32_bits(adev->vcn.inst->fw_shared.gpu_addr));
379 upper_32_bits(adev->vcn.inst->fw_shared.gpu_addr));
415 lower_32_bits(adev->vcn.inst->gpu_addr), 0, indirect);
418 upper_32_bits(adev->vcn.inst->gpu_addr),
[all...]
H A Dvcn_sw_ring.c51 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
52 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
H A Dvce_v4_0.c157 uint64_t addr = table->gpu_addr;
235 lower_32_bits(ring->gpu_addr));
237 upper_32_bits(ring->gpu_addr));
263 adev->vce.gpu_addr >> 8);
266 (adev->vce.gpu_addr >> 40) & 0xff);
273 adev->vce.gpu_addr >> 8);
276 (adev->vce.gpu_addr >> 40) & 0xff);
279 adev->vce.gpu_addr >> 8);
282 (adev->vce.gpu_addr >> 40) & 0xff);
345 WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_BASE_LO), ring->gpu_addr);
[all...]
H A Dvcn_v1_0.c326 lower_32_bits(adev->vcn.inst->gpu_addr));
328 upper_32_bits(adev->vcn.inst->gpu_addr));
338 lower_32_bits(adev->vcn.inst->gpu_addr + offset));
340 upper_32_bits(adev->vcn.inst->gpu_addr + offset));
346 lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
348 upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
396 lower_32_bits(adev->vcn.inst->gpu_addr), 0xFFFFFFFF, 0);
398 upper_32_bits(adev->vcn.inst->gpu_addr), 0xFFFFFFFF, 0);
408 lower_32_bits(adev->vcn.inst->gpu_addr + offset), 0xFFFFFFFF, 0);
410 upper_32_bits(adev->vcn.inst->gpu_addr
[all...]
H A Damdgpu_uvd.h43 uint64_t gpu_addr; member in struct:amdgpu_uvd_inst
H A Damdgpu_vce.h37 uint64_t gpu_addr; member in struct:amdgpu_vce
H A Dvcn_v4_0.c393 lower_32_bits(adev->vcn.inst[inst].gpu_addr));
395 upper_32_bits(adev->vcn.inst[inst].gpu_addr));
403 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset));
405 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset));
411 lower_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
413 upper_32_bits(adev->vcn.inst[inst].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
419 lower_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr));
421 upper_32_bits(adev->vcn.inst[inst].fw_shared.gpu_addr));
466 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);
469 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr),
[all...]
H A Dvcn_v4_0_3.c353 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr));
356 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr));
365 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset));
367 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset));
374 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset +
377 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset +
386 lower_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr));
389 upper_32_bits(adev->vcn.inst[inst_idx].fw_shared.gpu_addr));
438 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);
441 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr),
[all...]
H A Dvcn_v2_5.c433 lower_32_bits(adev->vcn.inst[i].gpu_addr));
435 upper_32_bits(adev->vcn.inst[i].gpu_addr));
444 lower_32_bits(adev->vcn.inst[i].gpu_addr + offset));
446 upper_32_bits(adev->vcn.inst[i].gpu_addr + offset));
452 lower_32_bits(adev->vcn.inst[i].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
454 upper_32_bits(adev->vcn.inst[i].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
460 lower_32_bits(adev->vcn.inst[i].fw_shared.gpu_addr));
462 upper_32_bits(adev->vcn.inst[i].fw_shared.gpu_addr));
497 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);
500 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr),
[all...]
/openbsd-current/sys/dev/pci/drm/amd/amdkfd/
H A Dkfd_mqd_manager.c58 mqd_mem_obj->gpu_addr = dev->dqm->hiq_sdma_mqd.gpu_addr;
84 mqd_mem_obj->gpu_addr = dev->dqm->hiq_sdma_mqd.gpu_addr + offset;
283 mqd_mem_obj->gpu_addr = dev->dqm->hiq_sdma_mqd.gpu_addr + offset;

Completed in 278 milliseconds

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