| /openbsd-current/sys/dev/pci/drm/amd/display/dc/dcn302/ |
| H A D | dcn302_hwseq.h | 31 void dcn302_dpp_pg_control(struct dce_hwseq *hws, unsigned int dpp_inst, bool power_on);
|
| H A D | dcn302_hwseq.c | 45 void dcn302_dpp_pg_control(struct dce_hwseq *hws, unsigned int dpp_inst, bool power_on) argument
55 switch (dpp_inst) {
|
| /openbsd-current/sys/dev/pci/drm/amd/display/dc/dcn303/ |
| H A D | dcn303_hwseq.h | 13 void dcn303_dpp_pg_control(struct dce_hwseq *hws, unsigned int dpp_inst, bool power_on);
|
| H A D | dcn303_hwseq.c | 27 void dcn303_dpp_pg_control(struct dce_hwseq *hws, unsigned int dpp_inst, bool power_on) argument
|
| /openbsd-current/sys/dev/pci/drm/amd/display/dc/dcn21/ |
| H A D | dcn21_dccg.c | 46 static void dccg21_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk) argument
88 REG_SET_2(DPPCLK_DTO_PARAM[dpp_inst], 0,
93 DPPCLK_DTO_ENABLE[dpp_inst], 1);
96 dccg->pipe_dppclk_khz[dpp_inst] = req_dppclk;
|
| /openbsd-current/sys/dev/pci/drm/amd/display/dc/dcn20/ |
| H A D | dcn20_dccg.c | 47 void dccg2_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk) argument
64 REG_SET_2(DPPCLK_DTO_PARAM[dpp_inst], 0,
68 DPPCLK_DTO_ENABLE[dpp_inst], 1);
71 DPPCLK_DTO_ENABLE[dpp_inst], 0);
74 dccg->pipe_dppclk_khz[dpp_inst] = req_dppclk;
|
| H A D | dcn20_hwseq.h | 98 unsigned int dpp_inst,
|
| H A D | dcn20_dccg.h | 304 void dccg2_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk);
|
| H A D | dcn20_hwseq.c | 434 unsigned int dpp_inst,
445 switch (dpp_inst) {
432 dcn20_dpp_pg_control( struct dce_hwseq *hws, unsigned int dpp_inst, bool power_on) argument
|
| /openbsd-current/sys/dev/pci/drm/amd/display/dc/dcn314/ |
| H A D | dcn314_hwseq.h | 46 void dcn314_dpp_root_clock_control(struct dce_hwseq *hws, unsigned int dpp_inst, bool clock_on);
|
| H A D | dcn314_dccg.c | 330 unsigned int dpp_inst,
335 if (dccg->dpp_clock_gated[dpp_inst] != clock_on)
340 REG_UPDATE(DPPCLK_DTO_CTRL, DPPCLK_DTO_ENABLE[dpp_inst], 0);
341 REG_SET_2(DPPCLK_DTO_PARAM[dpp_inst], 0,
346 REG_UPDATE(DPPCLK_DTO_CTRL, DPPCLK_DTO_ENABLE[dpp_inst], 1);
347 REG_SET_2(DPPCLK_DTO_PARAM[dpp_inst], 0,
352 dccg->dpp_clock_gated[dpp_inst] = !clock_on;
328 dccg314_dpp_root_clock_control( struct dccg *dccg, unsigned int dpp_inst, bool clock_on) argument
|
| H A D | dcn314_hwseq.c | 422 void dcn314_dpp_root_clock_control(struct dce_hwseq *hws, unsigned int dpp_inst, bool clock_on) argument
429 hws->ctx->dc->res_pool->dccg, dpp_inst, clock_on);
|
| /openbsd-current/sys/dev/pci/drm/amd/display/dc/inc/hw/ |
| H A D | dccg.h | 89 int dpp_inst,
173 unsigned int dpp_inst,
|
| /openbsd-current/sys/dev/pci/drm/amd/display/dc/dcn201/ |
| H A D | dcn201_dccg.c | 47 static void dccg201_update_dpp_dto(struct dccg *dccg, int dpp_inst, argument
|
| /openbsd-current/sys/dev/pci/drm/amd/display/dc/inc/ |
| H A D | hw_sequencer_private.h | 120 unsigned int dpp_inst,
123 unsigned int dpp_inst,
|
| /openbsd-current/sys/dev/pci/drm/amd/display/dc/dcn31/ |
| H A D | dcn31_dccg.c | 46 void dccg31_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk) argument
50 if (dccg->dpp_clock_gated[dpp_inst]) {
71 REG_SET_2(DPPCLK_DTO_PARAM[dpp_inst], 0,
75 DPPCLK_DTO_ENABLE[dpp_inst], 1);
78 DPPCLK_DTO_ENABLE[dpp_inst], 0);
80 dccg->pipe_dppclk_khz[dpp_inst] = req_dppclk;
|
| H A D | dcn31_dccg.h | 199 int dpp_inst,
|
| /openbsd-current/sys/dev/pci/drm/amd/display/dc/dce/ |
| H A D | dmub_replay.c | 175 copy_settings_data->dpp_inst = pipe_ctx->plane_res.dpp->inst;
177 copy_settings_data->dpp_inst = 0;
|
| H A D | dmub_psr.c | 346 copy_settings_data->dpp_inst = pipe_ctx->plane_res.dpp->inst;
348 copy_settings_data->dpp_inst = 0;
|
| /openbsd-current/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn20/ |
| H A D | dcn20_clk_mgr.c | 111 int dpp_inst, dppclk_khz, prev_dppclk_khz; local
116 dpp_inst = i;
123 clk_mgr->dccg, dpp_inst, dppclk_khz);
|
| /openbsd-current/sys/dev/pci/drm/amd/display/dc/dcn10/ |
| H A D | dcn10_hw_sequencer.h | 92 unsigned int dpp_inst,
|
| H A D | dcn10_hw_sequencer.c | 612 * @dpp_inst: DPP instance reference.
619 unsigned int dpp_inst,
630 switch (dpp_inst) {
617 dcn10_dpp_pg_control( struct dce_hwseq *hws, unsigned int dpp_inst, bool power_on) argument
|
| /openbsd-current/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn21/ |
| H A D | rn_clk_mgr.c | 114 int dpp_inst, dppclk_khz, prev_dppclk_khz; local
119 dpp_inst = clk_mgr->base.ctx->dc->res_pool->dpps[i]->inst;
122 prev_dppclk_khz = clk_mgr->dccg->pipe_dppclk_khz[dpp_inst];
126 clk_mgr->dccg, dpp_inst, dppclk_khz);
|
| /openbsd-current/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/ |
| H A D | dcn32_clk_mgr.c | 300 int dpp_inst = 0, dppclk_khz, prev_dppclk_khz; local
305 dpp_inst = context->res_ctx.pipe_ctx[i].plane_res.dpp->inst;
323 clk_mgr->dccg, dpp_inst, dppclk_khz);
|
| /openbsd-current/sys/dev/pci/drm/amd/display/dmub/inc/ |
| H A D | dmub_cmd.h | 2170 uint8_t dpp_inst; member in struct:dmub_cmd_psr_copy_settings_data
2813 uint8_t dpp_inst; member in struct:dmub_cmd_replay_copy_settings_data
|