Searched refs:dcfclk_mhz (Results 1 - 25 of 27) sorted by relevance

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/openbsd-current/sys/dev/pci/drm/amd/display/dc/dml/dcn321/
H A Ddcn321_fpu.c109 .dcfclk_mhz = 1434.0,
164 if (entry->dcfclk_mhz > 0) {
165 float bw_on_sdp = entry->dcfclk_mhz * dcn3_21_soc.return_bus_width_bytes * ((float)dcn3_21_soc.pct_ideal_sdp_bw_after_urgent / 100);
173 entry->dcfclk_mhz = bw_on_fabric / (dcn3_21_soc.return_bus_width_bytes * ((float)dcn3_21_soc.pct_ideal_sdp_bw_after_urgent / 100));
181 entry->dcfclk_mhz = bw_on_dram / (dcn3_21_soc.return_bus_width_bytes * ((float)dcn3_21_soc.pct_ideal_sdp_bw_after_urgent / 100));
197 sdp_bw_kbytes_sec = entry->dcfclk_mhz * dcn3_21_soc.return_bus_width_bytes * ((float)dcn3_21_soc.pct_ideal_sdp_bw_after_urgent / 100);
281 if (table[k].dcfclk_mhz > table[k+1].dcfclk_mhz)
323 if (max_clk_limit->dcfclk_mhz != 0)
324 curr_clk_limit->dcfclk_mhz
698 unsigned int dcfclk_mhz[DC__VOLTAGE_STATES] = {0}; local
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/openbsd-current/sys/dev/pci/drm/amd/display/dc/dml/dcn303/
H A Ddcn303_fpu.c196 unsigned int dcfclk_mhz[DC__VOLTAGE_STATES] = {0}; local
220 if (bw_params->clk_table.entries[i].dcfclk_mhz > max_dcfclk_mhz)
221 max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz;
230 max_dcfclk_mhz = dcn3_03_soc.clock_limits[0].dcfclk_mhz;
258 if (optimal_dcfclk_for_uclk[i] < bw_params->clk_table.entries[0].dcfclk_mhz)
259 optimal_dcfclk_for_uclk[i] = bw_params->clk_table.entries[0].dcfclk_mhz;
278 dcfclk_mhz[num_states] = dcfclk_sta_targets[i];
282 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j];
292 dcfclk_mhz[num_states] = dcfclk_sta_targets[i];
298 dcfclk_mhz[num_state
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/openbsd-current/sys/dev/pci/drm/amd/display/dc/dml/dcn302/
H A Ddcn302_fpu.c200 unsigned int dcfclk_mhz[DC__VOLTAGE_STATES] = {0}; local
224 if (bw_params->clk_table.entries[i].dcfclk_mhz > max_dcfclk_mhz)
225 max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz;
234 max_dcfclk_mhz = dcn3_02_soc.clock_limits[0].dcfclk_mhz;
264 if (optimal_dcfclk_for_uclk[i] < bw_params->clk_table.entries[0].dcfclk_mhz)
265 optimal_dcfclk_for_uclk[i] = bw_params->clk_table.entries[0].dcfclk_mhz;
284 dcfclk_mhz[num_states] = dcfclk_sta_targets[i];
288 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j];
297 dcfclk_mhz[num_states] = dcfclk_sta_targets[i];
303 dcfclk_mhz[num_state
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/openbsd-current/sys/dev/pci/drm/amd/display/dc/dml/dcn30/
H A Ddcn30_fpu.h63 unsigned int *dcfclk_mhz,
H A Ddcn30_fpu.c425 pipes[0].clks_cfg.dcfclk_mhz = dcfclk;
435 pipes[0].clks_cfg.dcfclk_mhz = context->bw_ctx.dml.soc.clock_limits[0].dcfclk_mhz;
451 pipes[0].clks_cfg.dcfclk_mhz = dcfclk;
606 dcn30_bb_max_clk->max_dcfclk_mhz = dcn3_0_soc.clock_limits[0].dcfclk_mhz;
642 unsigned int *dcfclk_mhz,
654 dcn3_0_soc.clock_limits[i].dcfclk_mhz = dcfclk_mhz[i];
655 dcn3_0_soc.clock_limits[i].fabricclk_mhz = dcfclk_mhz[i];
639 dcn30_fpu_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params, struct dc_bounding_box_max_clk *dcn30_bb_max_clk, unsigned int *dcfclk_mhz, unsigned int *dram_speed_mts) argument
/openbsd-current/sys/dev/pci/drm/amd/display/dc/dml/dcn301/
H A Ddcn301_fpu.c119 .dcfclk_mhz = 400.0,
131 .dcfclk_mhz = 400.0,
143 .dcfclk_mhz = 608.0,
155 .dcfclk_mhz = 676.0,
167 .dcfclk_mhz = 810.0,
304 pipes[0].clks_cfg.dcfclk_mhz = dml->soc.clock_limits[vlevel].dcfclk_mhz;
344 if ((unsigned int) dcn3_01_soc.clock_limits[j].dcfclk_mhz <= clk_table->entries[i].dcfclk_mhz) {
351 s[i].dcfclk_mhz
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/openbsd-current/sys/dev/pci/drm/amd/display/dc/dml/dcn314/
H A Ddcn314_fpu.c218 if ((unsigned int) dcn3_14_soc.clock_limits[j].dcfclk_mhz <= clk_table->entries[i].dcfclk_mhz) {
231 clock_limits[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz;
233 clock_limits[i].dcfclk_mhz < dcn3_14_soc.clock_limits[closest_clk_lvl].dcfclk_mhz) {
235 clock_limits[i].dcfclk_mhz = dcn3_14_soc.clock_limits[closest_clk_lvl].dcfclk_mhz;
/openbsd-current/sys/dev/pci/drm/amd/amdgpu/
H A Damdgpu_socbb.h29 uint32_t dcfclk_mhz; member in struct:gpu_info_voltage_scaling_v1_0
/openbsd-current/sys/dev/pci/drm/amd/display/dc/dml/dcn32/
H A Ddcn32_fpu.c120 .dcfclk_mhz = 1564.0,
182 uint16_t min_dcfclk_mhz = clk_mgr->base.bw_params->clk_table.entries[0].dcfclk_mhz;
184 uint16_t dcfclk_mhz_for_the_second_state = clk_mgr->base.ctx->dc->dml.soc.clock_limits[2].dcfclk_mhz;
192 clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.min_dcfclk = clk_mgr->base.bw_params->clk_table.entries[0].dcfclk_mhz;
450 sdp_bw_kbytes_sec = entry->dcfclk_mhz *
467 if (entry->dcfclk_mhz > 0) {
468 float bw_on_sdp = entry->dcfclk_mhz * dcn3_2_soc.return_bus_width_bytes * ((float)dcn3_2_soc.pct_ideal_sdp_bw_after_urgent / 100);
476 entry->dcfclk_mhz = bw_on_fabric / (dcn3_2_soc.return_bus_width_bytes * ((float)dcn3_2_soc.pct_ideal_sdp_bw_after_urgent / 100));
484 entry->dcfclk_mhz = bw_on_dram / (dcn3_2_soc.return_bus_width_bytes * ((float)dcn3_2_soc.pct_ideal_sdp_bw_after_urgent / 100));
578 pipes[0].clks_cfg.dcfclk_mhz
2787 unsigned int dcfclk_mhz[DC__VOLTAGE_STATES] = {0}; local
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/openbsd-current/sys/dev/pci/drm/amd/display/dc/dml/dcn31/
H A Ddcn31_fpu.c506 pipes[0].clks_cfg.dcfclk_mhz = dcfclk;
612 if ((unsigned int) dcn3_1_soc.clock_limits[j].dcfclk_mhz <= clk_table->entries[i].dcfclk_mhz) {
621 s[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz;
689 dcn3_15_soc.clock_limits[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz;
751 if ((unsigned int) dcn3_16_soc.clock_limits[j].dcfclk_mhz <=
752 clk_table->entries[i].dcfclk_mhz) {
766 s[i].dcfclk_mhz
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/openbsd-current/sys/dev/pci/drm/amd/display/dc/dml/dcn20/
H A Ddcn20_fpu.c223 .dcfclk_mhz = 560.0,
234 .dcfclk_mhz = 694.0,
245 .dcfclk_mhz = 875.0,
256 .dcfclk_mhz = 1000.0,
267 .dcfclk_mhz = 1200.0,
279 .dcfclk_mhz = 1200.0,
334 .dcfclk_mhz = 560.0,
345 .dcfclk_mhz = 694.0,
356 .dcfclk_mhz = 875.0,
367 .dcfclk_mhz
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/openbsd-current/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn314/
H A Ddcn314_clk_mgr.c459 bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1;
462 bw_params->clk_table.entries[i].dcfclk_mhz;
614 if (bw_params->clk_table.entries[j].dcfclk_mhz <= clock_table->DcfClocks[i])
625 bw_params->clk_table.entries[i].dcfclk_mhz = clock_table->DcfClocks[i];
641 bw_params->clk_table.entries[i].dcfclk_mhz = find_max_clk_value(clock_table->DcfClocks, NUM_DCFCLK_DPM_LEVELS);
670 if (!bw_params->clk_table.entries[i].dcfclk_mhz)
671 bw_params->clk_table.entries[i].dcfclk_mhz = def_max.dcfclk_mhz;
685 ASSERT(bw_params->clk_table.entries[i-1].dcfclk_mhz);
/openbsd-current/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn315/
H A Ddcn315_clk_mgr.c404 bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1;
407 bw_params->clk_table.entries[i].dcfclk_mhz;
504 if (bw_params->clk_table.entries[j].dcfclk_mhz <= clock_table->DcfClocks[i])
514 bw_params->clk_table.entries[i].dcfclk_mhz = clock_table->DcfClocks[i];
526 bw_params->clk_table.entries[i].dcfclk_mhz = clock_table->DcfClocks[0];
546 if (!bw_params->clk_table.entries[i].dcfclk_mhz)
547 bw_params->clk_table.entries[i].dcfclk_mhz = def_max.dcfclk_mhz;
566 ASSERT(bw_params->clk_table.entries[i-1].dcfclk_mhz);
/openbsd-current/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn301/
H A Dvg_clk_mgr.c409 bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1;
412 bw_params->clk_table.entries[i].dcfclk_mhz;
497 .dcfclk_mhz = 400,
504 .dcfclk_mhz = 483,
511 .dcfclk_mhz = 602,
518 .dcfclk_mhz = 738,
590 bw_params->clk_table.entries[i].dcfclk_mhz = find_dcfclk_for_voltage(clock_table, clock_table->DfPstateTable[j].voltage);
595 bw_params->clk_table.entries[i].dcfclk_mhz = find_max_clk_value(clock_table->DcfClocks, VG_NUM_DCFCLK_DPM_LEVELS);
/openbsd-current/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn21/
H A Drn_clk_mgr.c477 ranges->reader_wm_sets[num_valid_sets].min_drain_clk_mhz = bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1;
479 ranges->reader_wm_sets[num_valid_sets].max_drain_clk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz;
580 .dcfclk_mhz = 400,
587 .dcfclk_mhz = 483,
594 .dcfclk_mhz = 602,
601 .dcfclk_mhz = 738,
668 bw_params->clk_table.entries[i].dcfclk_mhz = find_dcfclk_for_voltage(clock_table, clock_table->FClocks[j].Vol);
/openbsd-current/sys/dev/pci/drm/amd/display/dc/inc/hw/
H A Dclk_mgr.h86 unsigned int dcfclk_mhz; member in struct:clk_limit_table_entry
/openbsd-current/sys/dev/pci/drm/amd/display/dc/dml/
H A Ddisplay_mode_structs.h159 double dcfclk_mhz; member in struct:_vcs_dpi_voltage_scaling_st
552 double dcfclk_mhz; member in struct:_vcs_dpi_display_clocks_and_cfg_st
H A Ddisplay_mode_lib.c281 dml_print("DML PARAMS: dcfclk_mhz = %3.2f\n", clks_cfg->dcfclk_mhz);
H A Ddisplay_mode_vba.c380 mode_lib->vba.DCFCLK = soc->clock_limits[i].dcfclk_mhz;
395 mode_lib->vba.DCFCLKPerState[i] = soc->clock_limits[i].dcfclk_mhz;
1093 mode_lib->vba.DCFCLK = mode_lib->vba.cache_pipes[0].clks_cfg.dcfclk_mhz;
/openbsd-current/sys/dev/pci/drm/amd/display/dc/dcn201/
H A Ddcn201_resource.c144 .dcfclk_mhz = 1000.0,
155 .dcfclk_mhz = 1000.0,
166 .dcfclk_mhz = 1000.0,
177 .dcfclk_mhz = 1000.0,
188 .dcfclk_mhz = 1000.0,
/openbsd-current/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn316/
H A Ddcn316_clk_mgr.c366 bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1;
369 bw_params->clk_table.entries[i].dcfclk_mhz;
534 bw_params->clk_table.entries[i].dcfclk_mhz = temp;
/openbsd-current/sys/dev/pci/drm/amd/display/dc/dcn30/
H A Ddcn30_resource.c2094 unsigned int dcfclk_mhz[DC__VOLTAGE_STATES] = {0}; local
2117 if (bw_params->clk_table.entries[i].dcfclk_mhz > dcn30_bb_max_clk.max_dcfclk_mhz)
2118 dcn30_bb_max_clk.max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz;
2155 if (optimal_dcfclk_for_uclk[i] < bw_params->clk_table.entries[0].dcfclk_mhz) {
2156 optimal_dcfclk_for_uclk[i] = bw_params->clk_table.entries[0].dcfclk_mhz;
2176 dcfclk_mhz[num_states] = dcfclk_sta_targets[i];
2180 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j];
2189 dcfclk_mhz[num_states] = dcfclk_sta_targets[i];
2195 dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j];
2201 dcn30_fpu_update_bw_bounding_box(dc, bw_params, &dcn30_bb_max_clk, dcfclk_mhz, dram_speed_mt
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/openbsd-current/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn31/
H A Ddcn31_clk_mgr.c444 bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1;
447 bw_params->clk_table.entries[i].dcfclk_mhz;
607 bw_params->clk_table.entries[i].dcfclk_mhz = find_clk_for_voltage(clock_table, clock_table->DcfClocks, clock_table->DfPstateTable[j].Voltage);
/openbsd-current/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn32/
H A Ddcn32_clk_mgr.c183 &clk_mgr_base->bw_params->clk_table.entries[0].dcfclk_mhz,
185 clk_mgr_base->bw_params->dc_mode_limit.dcfclk_mhz = dcn30_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_DCFCLK);
/openbsd-current/sys/dev/pci/drm/amd/display/dc/clk_mgr/dcn30/
H A Ddcn30_clk_mgr.c133 &clk_mgr_base->bw_params->clk_table.entries[0].dcfclk_mhz,

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