Searched refs:cp_int_cntl (Results 1 - 10 of 10) sorted by relevance
/openbsd-current/sys/dev/pci/drm/radeon/ |
H A D | ni.h | 32 int ring, u32 cp_int_cntl);
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H A D | evergreen.c | 4496 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE; local 4527 cp_int_cntl |= TIME_STAMP_INT_ENABLE; 4540 cp_int_cntl |= RB_INT_ENABLE; 4541 cp_int_cntl |= TIME_STAMP_INT_ENABLE; 4564 cayman_cp_int_cntl_setup(rdev, 0, cp_int_cntl); 4568 WREG32(CP_INT_CNTL, cp_int_cntl);
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H A D | ni.c | 1380 int ring, u32 cp_int_cntl) 1383 WREG32(CP_INT_CNTL, cp_int_cntl); 1379 cayman_cp_int_cntl_setup(struct radeon_device *rdev, int ring, u32 cp_int_cntl) argument
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H A D | r600.c | 3763 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE; local 3821 cp_int_cntl |= RB_INT_ENABLE; 3822 cp_int_cntl |= TIME_STAMP_INT_ENABLE; 3873 WREG32(CP_INT_CNTL, cp_int_cntl);
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H A D | si.c | 6052 u32 cp_int_cntl; local 6070 cp_int_cntl = RREG32(CP_INT_CNTL_RING0) & 6082 cp_int_cntl |= TIME_STAMP_INT_ENABLE; 6102 WREG32(CP_INT_CNTL_RING0, cp_int_cntl);
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H A D | cik.c | 7017 u32 cp_int_cntl; local 7037 cp_int_cntl = RREG32(CP_INT_CNTL_RING0) & 7039 cp_int_cntl |= PRIV_INSTR_INT_ENABLE | PRIV_REG_INT_ENABLE; 7063 cp_int_cntl |= TIME_STAMP_INT_ENABLE; 7217 WREG32(CP_INT_CNTL_RING0, cp_int_cntl);
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/openbsd-current/sys/dev/pci/drm/amd/amdgpu/ |
H A D | gfx_v6_0.c | 3202 u32 cp_int_cntl; local 3206 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 3207 cp_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK; 3208 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 3211 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 3212 cp_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK; 3213 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 3224 u32 cp_int_cntl; local 3228 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING1); 3229 cp_int_cntl 3265 u32 cp_int_cntl; local 3290 u32 cp_int_cntl; local [all...] |
H A D | gfx_v7_0.c | 4663 u32 cp_int_cntl; local 4667 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 4668 cp_int_cntl &= ~CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK; 4669 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 4672 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 4673 cp_int_cntl |= CP_INT_CNTL_RING0__TIME_STAMP_INT_ENABLE_MASK; 4674 WREG32(mmCP_INT_CNTL_RING0, cp_int_cntl); 4737 u32 cp_int_cntl; local 4741 cp_int_cntl = RREG32(mmCP_INT_CNTL_RING0); 4742 cp_int_cntl 4762 u32 cp_int_cntl; local [all...] |
H A D | gfx_v11_0.c | 5719 uint32_t cp_int_cntl, cp_int_cntl_reg; local 5740 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 5741 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 5743 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 5745 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 5748 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 5749 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING [all...] |
H A D | gfx_v10_0.c | 8766 uint32_t cp_int_cntl, cp_int_cntl_reg; local 8787 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 8788 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 8790 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl); 8793 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg); 8794 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, 8796 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
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