Searched refs:cfgcr0 (Results 1 - 4 of 4) sorted by relevance

/openbsd-current/sys/dev/pci/drm/i915/display/
H A Dintel_dpll_mgr.h208 u32 cfgcr0; member in struct:intel_dpll_hw_state
218 * u32 cfgcr0, cfgcr1;
H A Dintel_dpll_mgr.c2730 dco_freq = (pll_state->cfgcr0 & DPLL_CFGCR0_DCO_INTEGER_MASK) *
2733 dco_fraction = (pll_state->cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >>
2756 pll_state->cfgcr0 = DPLL_CFGCR0_DCO_FRACTION(dco_fraction) |
3553 hw_state->cfgcr0 = intel_de_read(dev_priv, ADLS_DPLL_CFGCR0(id));
3556 hw_state->cfgcr0 = intel_de_read(dev_priv, DG1_DPLL_CFGCR0(id));
3559 hw_state->cfgcr0 = intel_de_read(dev_priv,
3564 hw_state->cfgcr0 = intel_de_read(dev_priv,
3575 hw_state->cfgcr0 = intel_de_read(dev_priv,
3580 hw_state->cfgcr0 = intel_de_read(dev_priv,
3640 intel_de_write(dev_priv, cfgcr0_reg, hw_state->cfgcr0);
[all...]
H A Dintel_display_debugfs.c667 seq_printf(m, " cfgcr0: 0x%08x\n", pll->state.hw_state.cfgcr0);
H A Dintel_display.c5325 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr0);

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